ICS1562B
User Programmable Differential Output Graphics Clock Generator
ICS1562B
TSD
DESCRIPTION
REG#
6
7
8
8
9
BIT(S)
0-3
0-3
3
0-2
0-1
BIT REF.
N2[0]..N2[3]
N2[4]..N2[7]
N2[8]
V[0]..V[1]
P[0]..P[1]
Sets the modulus of the N2 divider.
The input of the N2 divider is the output of the N1 divider in all clock
modes except AUXEN.
Sets the gain of the VCO.
Sets the gain of the phase detector according to this table.
V[2]
1
1
1
1
V[1]
0
0
1
1
V[0]
0
1
0
1
VCO GAIN
(MHz/VOLT)
30
45
60
80
9
3
[P2]
Phase detector tuning bit. Normally should be set to one.
P[1]
0
0
1
1
P[0]
0
1
0
1
GAIN (uA/radian)
0.05
0.15
0.5
1.5
10
10
10
1
2
3
LOADEN~
SKEW-
SKEW+
Load clock divider enable (active low). When set to logic 1, the
LOAD and LD/N2 outputs will cease toggling.
Differential output duty factor adjust.
SKEW+
0
0
1
1
SKEW-
0
1
0
1
Default
Reduces T
HIGH
by approximately
100 ps
Increases T
HIGH
by approximately
100 ps
Do not use
9
IDT™ / ICS™
User Programmable Differential Output Graphics Clock Generator
9
ICS1562B
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
