ICS1562B
ICS1562B
User Programmable Differential Output Graphics Clock Generator
TSD
Register Mapping - ICS1562B-201 (Serial Programming Option)
NOTE: IT IS NOT NECESSARY TO UNDERSTAND THE FUNCTION OF THESE BITS TO USE THE ICS1562B. PC SOFTWARE IS AVAILABLE
FROM ICS TO AUTOMATICALLY GENERATE ALL REGISTER VALUES BASED ON REQUIREMENTS. CONTACT FACTORY FOR DETAILS.
BIT(S)
1-4
BIT REF.
DESCRIPTION
N1[0]..N1[3]
Sets N1 modulus according to this table. These bits are set to implement
a divide-by-four on power-up.
N1[3]
N1[2]
N1[1]
N1[0]
RATIO
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
3
4
0
4
0
5
1
6
1
8
1
8
1
10
12
16
16
20
X
X
X
X
5
6
RESERVED
JAMPLL
Must be set to zero.
Tristates phase detector outputs, resets phase detector logic, and resets
R, A, M, and N2 counters.
7
DACRST
Set to zero for normal operations. When set to one, the CLK+ output is
kept high and the CLK- output is kept low. (All other device functions are
unaffected.) When returned to zero, the CLK+ and CLK- outputs will
resume toggling on a rising edge of the LD output (+/−1 CLK period).
To initiate a RAMDAC reset sequence, simply write a one to this register
bit followed by a zero.
8
9
SELXTAL
ALTLOOP
When set to logic 1, passes the reference frequency to the post-scaler.
Controls substitution of N1 and N2 dividers into feedback loop of PLL.
When this bit is a logic 1, the N1 and N2 dividers are used.
10
11
12
SCEN
VRAM shift clock enable bit. When logic 1, the BLANK pin can be used
to disable the LD/N2 output.
EXTFBKEN
PDRSTEN
External PLL feedback select. When logic 1, the EXTFBK pin is used for
the phase-frequency detector feedback input.
Phase detector reset enable control bit. When this bit is set, a high level
on the BLANK input will disable PLL locking. See "Internal Feedback
Operation" section for more details on the operation of this function.
11
IDT™ / ICS™ User Programmable Differential Output Graphics Clock Generator
ICS1562B
11
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
