ICS1562B
ICS1562B
User Programmable Differential Output Graphics Clock Generator
TSD
BIT(S)
33-38
BIT REF.
DESCRIPTION
M[0]..M[5]
M counter control bits
Modulus = value +1
39
FBKPOL
External feedback polarity control bit. The PLL will lock to the falling
edge of EXTFBK when FBKPOL=1 and to the rising edge of EXTFBK
when FBKPOL=0.
40
DBLFREQ
A[0]..A[3]
Doubles modulus of dual-modulus prescaler (from 6/7 to 12/14).
41-44
Controls A counter. When set to zero, modulus=7. Otherwise,
modulus=7 for “value” underflows of the prescaler, and modulus=6
thereafter until M counter underflows.
45
46
RESERVED
LOADEN~
Set to zero.
Load clock divider enable (active low). When set to logic 1, the LOAD
and LD/N2 outputs will cease toggling.
47
48
SKEW-
SKEW+
Differential output duty factor adjust.
SKEW+
SKEW-
0
0
0
1
Default
Reduces THIGH by approximately
100 ps
1
1
0
1
Increases THIGH by approximately
100 ps
Do not use
49-55
56
R[0]..R[6]
REFPOL
Reference divider modulus control bits
Modulus = value + 1
PLL locks to the rising edge of XTAL1 input when REFPOL=1 and to
the falling edge of XTAL1 when REFPOL=0.
13
IDT™ / ICS™ User Programmable Differential Output Graphics Clock Generator
ICS1562B
13
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
