ICS1523
2
Video Clock Synthesizer with I C Programmable Delay
Parameter
Symbol
Min.
Max.
Units
Notes
Analog Input (HSYNC)
Input High Voltage
V
1.7
VSS - 0.3
2
5.5
1.1
V
V
IH
Input Low Voltage
V
IL
Digital Inputs (SDA, SCL, EXTFB, OSC, I CADDR)
Input High Voltage
Input Low Voltage
Input Hysteresis
POR Threshold
V
2
VSS - 0.3
0.2
5.5
0.8
0.6
1.8
V
V
V
V
IH
V
IL
-
-
VSS
Voltage that resets
register values
SDA Digital Output
SDA Output Low Voltage
SDA Output High Voltage
V
0.4
6.0
V
V
IOUT = 3ma
OL
V
Determined by
external Rset
resistor
OH
PECL Outputs (CLK+, CLK-, CLK/2+, CLK/2-)
Output High Voltage
V
-
-
VDD
250
-
V
MHz
V
IOUT=0
OH
Maximum Output Frequency
Output Low Voltage *
F MAX
VDDD = 3.3 V
P
V
1.0
IOUT =
OL
Programmed Value
1
Duty Cycle
P
T
45
-
55
1.0
1.2
%
ns
ns
2
2
2
DC
Transition Time - Rise
Transition Time - Fall
PR
T
-
PF
SSTL_3 Outputs (CLK, CLK/2, FUNC, LOCK/REF)
Output Resistance
Maximum Output Frequency
Duty Cycle
R
-
-
80
150
55
Ω
MHz
%
1 V < V < 2 V
O
O
F MAX
VDDD = 3.3 V
s
S
T
45
-
3
3
DC
CR
Clock and FUNC
1.6
ns
Transition Time - Rise
Clock and FUNC
Transition Time - Fall
T
T
-
-
-
1.0
3.0
2.0
ns
ns
ns
3
3
3
CF
LR
LOCK/REF Transition Time -
Rise
LOCK/REF Transition Time - Fall
T
LF
Note 1- V must not fall below the level given so that the correct value for IOUT can be maintained.
OL
o
Note 2- Measured at 135MHz, 3.6 VDC, 0 C, 20 pF, with 75 Ω Termination.
o
Note 3- Measured at 135MHz, 3.6 VDC, 0 C, 20 pF, Unterminated.
MDS ICS1523 ZB
19
Revision 051310
Integrated Device Technology, Inc.ꢀ Tech Support: www.idt.com/go/clockhelp
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