ICS1523
2
Video Clock Synthesizer with I C Programmable Delay
12.2 Timing for 0x0:2=1
Figure 12-3 0x0:2=1 Timing Diagram
Table 12-3 0x0:2=1 Timing Values
Symbol Parameter
Minimum Typical Maximum Units
T2
T3
HSYNC Low to FUNC High Delay
T8 + T3
10
ns
ns
HSYNC Low to PECL CLK+ High Delay
(DPA Offset = 0)
-
-
T4
T5
T6
T7
T8
PECL Clock to SSTL_3 Clock Delay
PECL Clock to FUNC Delay
PECL Clock to PECL/2 Clock
PECL Clock to SSTL_3 CLK/2 Delay
PECL Clock High Time
0
0.2
1.0
1.0
0.9
0.5
0.6
1.6
1.6
1.2
-
ns
ns
ns
ns
UI
0.6
0.6
0.4
-
MDS ICS1523 ZB
16
Revision 051310
Integrated Device Technology, Inc.ꢀ Tech Support: www.idt.com/go/clockhelp