ICS1523
2
Video Clock Synthesizer with I C Programmable Delay
12.3 HSYNC to REF Timing
Figure 12-4 HSYNC to REF Timing Diagram
HSYNC
Reg0:2 = 1
t0
t1
REF
HSYNC
Reg0:2 = 0
t0
t1
REF
Table 12-4 HSYNC to REF Timing Diagram
Symbol Parameter
Minimum Typical Maximum
Units
ns
T
T
HSYNC Low to REF Delay
HSYNC High to REF Delay
6
7.5
4.3
8.5
6
0
1
3.5
ns
12.4 CLK/2 Timing for Odd and Even Feedback Divider
Figure 12-5 CLK/2: Even versus Odd
FUNC
Even - Reg2:0=0
CLK/2
Odd - Reg2:0=1
CLK/2
For simplicity, the waveforms drawn show only the identical PECL CLK/2+ and the SSTL_3 CLK/2 signals. CLK/2-
is the compliment of the CLK/2+ signal.
Note that regardless of the CLK\2 phase at the assertion of FUNC, the clocks always have the same phase at the
fall of FUNC, regardless of 0x2
MDS ICS1523 ZB
17
Revision 051310
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