ICS1523
2
Video Clock Synthesizer with I C Programmable Delay
12.1 Timing for 0x0:2=0
Figure 12-2 0x0:2=0 Timing Diagram
Table 12-2 0x0:2=0 Timing Values
Symbol Parameter
Minimum Typical Maximum Units
T2
T3
T4
HSYNC High to FUNC High
(DPA Offset = 0)
T8 + T3
ns
ns
ns
HSYNC High to PECL CLK+ High
(DPA Offset = 0)
-
7
-
PECL Clock Low to SSTL_3 Clock Low
Delay
0
0.2
0.6
T5
T6
T7
T8
PECL Clock Low to FUNC High Delay
PECL Clock Low to PECL/2 High Clock
PECL Clock Low to SSTL_3 CLK/2 Delay
PECL Clock High Time
0.6
0.6
0.4
-
1.0
1.0
0.9
0.5
1.6
1.6
1.2
-
ns
ns
ns
UI
MDS ICS1523 ZB
15
Revision 051310
Integrated Device Technology, Inc.ꢀ Tech Support: www.idt.com/go/clockhelp
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
