ICS1523
2
Video Clock Synthesizer with I C Programmable Delay
11.2 Programming Flow for Modifying PLL and DPA Settings
BEGIN
Determine Horizontal Total
HTOTAL
Program Input Control Register Reg0x0
Typically = 41h
(Coast disabled, Positive edge of HSYNC, Internal Feedback,
FUNC = regenerated HSYNC, PLL lock status to LOCK (STATUS) pin
Program Loop Control Register Reg0x1
VCO Divider 0x1:5~4 = (Maximum value where
Required Output Frequency * VCOD < 500 MHz)
Typical Charge Pump Current 0x1:2~0= 011b
Program Feedback Divider Reg0x2, Reg0x3
Internal Feedback Divider (0x3 & 0x2) = HTOTAL - 8
Program Internal Filter Reg0x4
Select Internal Filter 0x4:7 = 1
Program DPA Reg0x5
DPA Resolution 0x5 = (Value From Note 8 Table)
DPA Offset, 0x4:5~0 = 0
Program Output Control Reg0x6
Enable the desired outputs
Program OSC Divider Reg0x7
Select Desired Input Reg0x7:7
Select OSC divider value (if needed)
Decrement Charge
Full S/W Reset
Pump Current
Reg0xA = 5Ah
Reg0x1:2~0
PLL LOCKED?
LOCK Pin or
No
Read 0x12:1
Yes
Increment DPA
Correct Phase
Relationship?
No
Offset
Reg0x4
Yes
END
MDS ICS1523 ZB
13
Revision 051310
Integrated Device Technology, Inc.ꢀ Tech Support: www.idt.com/go/clockhelp
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
