ICS1523
2
Video Clock Synthesizer with I C Programmable Delay
Section 12 Timing Diagrams
Figure 12-1 DPA Operation
HSYNC
Fixed delay −See Figure 12-2 and Figure 12-3
One full speed clock period
DPA Offset when
DPA_OS [5-0] = 0
1 unit of DPA delay
DPA Offset when
DPA_OS [5-0] = 1
2 units of DPA delay
DPA Offset when
DPA_OS [5-0] = 2
1 unit of DPA delay
.
.
.
Maximum units of DPA delay
DPA Offset when
DPA_OS [5-0] = Max
DPA Offset = CLK Period * (# of DPA Elements Selected [0x4:4~0]
(# of DPA Elements Available)[0x5:1-0]
Table 12-1 DPA Offset Ranges
0x4:5-0
Maximum
DPA Clock Range in MHz
Register 5
Selected #
of DPA
Elements
0F
Total # of DPA
Min
Max
1~0
Elements
00
16
48
24
12
160
80
1F
3F
01
11
32
64
40
Using the DPA above 160 MHz is not recommended. Set DPA_OS = 0 for speeds in excess of 160 MHz to bypass
the DPA. The DPA Resolution Select register (0x5:0~1) is double-buffered. Working registers are loaded only after
a DPA Software reset (0x8=xA)
MDS ICS1523 ZB
14
Revision 051310
Integrated Device Technology, Inc.ꢀ Tech Support: www.idt.com/go/clockhelp
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
