IC80C51
IC80C31
Thus, the processor acknowledges an interrupt request by
executing a hardware-generated LCALL to the appropriate
servicing routine. In some cases it also clears the flag that
generated the interrupt, and in other cases it does not. It
never clears the Serial Port or Timer 2 flags. This must be
done in the user's software. The processor clears an
external interrupt flag (IE0 or IE1) only if it was transition-
activated. The hardware-generated LCALL pushes the
contents of the Program Counter onto the stack (but it does
not save the PSW) and reloads the PC with an address that
depends on the source of the interrupt being serviced, as
shown in the following table.
When an interrupt is accepted, the following action occurs:
1. The current instruction completes operation.
2. The PC is saved on the stack.
3. The current interrupt status is saved internally.
4. Interrupts are blocked at the level of the interrupts.
5. The PC is loaded with the vector address of the ISR
(interrupts service routine).
6. The ISR executes.
The ISR executes and takes action in response to the
interrupt. The ISR finishes with RETI (return from interrupt)
instruction. This retrieves the old value of the PC from the
stack and restores the old interrupt status. Execution of the
main program continues where it left off.
Interrupt
Source
Interrupt
Request Bits
Cleared by
Hardware
Vector
Address
INT0
IE0
No (level)
0003H
Yes (trans.)
Timer 0
TF0
IE1
Yes
000BH
0013H
External Interrupts
INT1
No (level)
The external sources can be programmed to be level-
activated or transition-activated by setting or clearing bit
IT1 or IT0 in Register TCON. If ITx= 0, external interrupt x
is triggered by a detected low at the INTx pin. If ITx = 1,
external interrupt x is edge-triggered. In this mode if
successive samples of the INTx pin show a high in one
cycle and a low in the next cycle, interrupt request flag IEx
in TCON is set. Flag bit IEx then requests the interrupt.
Yes (trans.)
Timer 1
Serial Port
Timer 2
TF1
RI, TI
Yes
No
001BH
0023H
002BH
0000H
TF2, EXF2
RST
No
System
Reset
Execution proceeds from that location until the RETI
instruction is encountered. The RETI instruction informs
the processor that this interrupt routine is no longer in
progress, then pops the top two bytes from the stack and
reloads the Program Counter. Execution of the interrupted
program continues from where it left off.
Since the external interrupt pins are sampled once each
machine cycle, an input high or low should hold for at least
12 oscillator periods to ensure sampling. If the external
interrupt is transition-activated, the external source has to
hold the request pin high for at least one machine cycle,
and then hold it low for at least one machine cycle to ensure
that the transition is seen so that interrupt request flag IEx
will be set. IEx will be automatically cleared by the CPU
when the service routine is called.
Note that a simple RET instruction would also have returned
execution to the interrupted program, but it would have left
the interrupt control system thinking an interrupt was still in
progress.
If the external interrupt is level-activated, the external
source has to hold the request active until the requested
interrupt is actually generated. Then the external source
must deactivate the request before the interrupt service
routine is completed, or else another interrupt will be
generated.
SFR Register and
Interrupt
External 0
External 1
Timer 1
Flag
IE0
IE1
TF1
TF0
TI
Bit Position
TCON.1
TCON.3
TCON.7
TCON.5
SCON.1
SCON.0
Timer 0
Serial Port
Serial Port
RI
S3-28
Integrated Circuit Solution Inc.
MC001-0B
ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
