IC80C51
IC80C31
IP:
Interrupt Priority Register. Bit Addressable.
TCON:
Timer/Counter Control Register. Bit Addressable
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
—
—
—
PS
PT1 PX1 PT0 PX0
TF1 TR1 TF0 TR0
Register Description:
IE1
IT1
IE0 IT0
Register Description:
—
—
—
PS
IP.7
IP.6
IP.5
IP.4
Not implemented, reserve for future use
TF1 TCON.7 Timer 1 overflow flag. Set by hardware
when the Timer/Counter 1 overflows.
(3)
Cleared by hardware as processor
vectors to the interrupt service routine.
Not implemented, reserve for future use
(3)
TR1 TCON.6 Timer 1 run control bit. Set/Cleared by
software to turn Timer/Counter 1 ON/
OFF.
Not implemented, reserve for future use
(3)
Defines Serial Port interrupt priority level
Defines Timer 1 interrupt priority level
Defines External Interrupt 1 priority level
Defines Timer 0 interrupt priority level
Defines External Interrupt 0 priority level
TF0 TCON.5 Timer 0 overflow flag. Set by hardware
when the Timer/Counter 0 overflows.
PT1 IP.3
PX1 IP.2
PT0 IP.1
PX0 IP.0
Notes:
Cleared by hardware as processor
vectors to the interrupt service routine.
TR0 TCON.4 Timer 0 run control bit. Set/Cleared by
software to turn Timer/Counter 0 ON/
OFF.
1. In order to assign higher priority to an interrupt the
coresponding bit in the IP register must be set to 1. While
an interrupt service is in progress, it cannot be inter-
rupted by a lower or same level interrupt.
IE1
TCON.3 External Interrupt 1 edge flag. Set by
hardware when the External Interrupt
edge is detected. Cleared by hardware
when interrupt is processed.
2. Priority within level is only to resolve simultaneous
requests of the same priority level. From high-to-low,
interrupt sources are listed below:
IE0
TF0
IE1
TF1
RI or TI
IT1
IE0
TCON.2 Interrupt 1 type control bit. Set/Cleared
by software specify falling edge/low level
triggered External Interrupt.
TCON.1 External Interrupt 0 edge flag. Set by
hardware when the External Interrupt
edge is detected. Cleared by hardware
when interrupt is processed.
3. User software should not write 1s to reserved bits. These
bits may be used in future products to invoke new features.
IT0
TCON.0 Interrupt 0 type control bit. Set/Cleared
by software specify falling edge/low level
triggered External Interrupt.
S3-12
Integrated Circuit Solution Inc.
MC001-0B
ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
