ICS9248-101
Functionality
VDD =3.3V±5%,VDDL=2.5V±5%or3.3±5%,TA=0to70°C
Crystal (X1, X2) = 14.31818MHz
CPU
(MHz)
124.00
120.00
114.99
109.99
105.00
83.31
137.00
75.00
100.00
95.00
83.31
133.33
90.00
96.22
66.82
PCI
(MHz)
41.33
40.00
38.33
36.66
35.00
41.65
34.25
37.50
33.33
31.67
27.77
33.33
30.00
32.07
33.41
30.5
FS3
FS2
FS1
FS0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
91.5
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Bit
Description
PWD
0 - ±0.25% Spread Spectrum Modulation, Center Spread
1 - 0 to -0.5% Down Spread
Bit 7
1
CPUCLK
(MHz)
PCICLK
(MHz)
Bit [2, 6:4]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
124.00
120.00
114.99
109.99
105.00
83.31
137.00
75.00
100.00
95.00
83.31
133.33
90.00
96.22
66.82
91.5
41.33
40.00
38.33
36.66
35.00
41.65
34.25
37.50
33.33
31.67
27.77
33.33
30.00
32.07
33.41
30.5
Note1
Bit
[2, 6:4]
Notes:
1, Default at Power-up will be for latched
logic inputs to define frequency. Bit [2,
6:4] are default to 0010.
0 - Frequency is selected by hardware select, latched inputs
1 - Frequency is selected by Bit [2, 6:4]
0 - Normal
1 - Spread Spectrum Enabled
0 - Running
Bit 3
Bit 1
Bit 0
0
1
0
2, PWD = Power-Up Default
3, When disabling spread spectrum bit7
needs to be set to 0 to maintain nominal
frequency.
1- Tristate all outputs
4
ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
