iC-MD RS-422 QUADRATURE
ENCODER RECEIVER/COUNTER WITH SPI AND BiSS
Rev A1, Page 17/23
TPS
Code
0
Addr. 0x49; bit 0
The status bit (EXTERR: external error) indicates if the
pin NERR was either pulled-down from outside or set
to 0 from inside (an internal masked error has ocurred).
Description
TPI pin at low
TPI pin at high
1
EXTERR
Addr. 0x49, 0x4A; bit 3
Description
Table 38: Touch-Probe Pin Status
Code
0
no external error
Status bit ENSSI signals if the SSI interface instead of
BiSS is configured. This is configured by the SLI pin,
if the pin is open, the SSI interface is selected. ENSSI
has an internal digital filter of 12.5 µs.
1
external error
Notes
Reset by reading Adr. 0x49 or 0x4A
Table 35: External Error
ENSSI
Addr. 0x4A; bit 0
Description
Code
The status bit (EXTWARN: external warning) bit indi-
cates if the pin NWARN was either pulled-down from
outside or set to 0 from inside (an internal masked
warning has ocurred).
0
1
SSI not enabled
SSI enabled (pin SLI open)
Table 39: Enable SSI
EXTWARN
Addr. 0x49, 0x4A; bit 2
Description
Error and warning mask
Code
0
no external warning
1
external warning
The masks (MASK) and not masks (NMASK) bits, stip-
ulate whether error and warning events are signaled
as an alarm via the open drain I/O pins NERR and
NWARN.
Notes
reset by reading Adr. 0x49 or 0x4A
Table 36: External Warning
MASK
Adr 0x02, bit 7:0; Adr 0x03, bit 1:0
Error/Warning Event
If BiSS/SSI and SPI try to access at the same time
to the internal data bus (BiSS register communication
and SPI communication) the bit COMCOL will be set
indicating that a collision has taken place. If SPICH is
activated (table 45), the writing process of AB via SPI
and reading of channel 0 via BiSS at the same time will
generates no COMCOL warning.
Bit
9
enable SSI (warning)
8
external error (error)
7
zero value of active counter 0, 1 or 2 (warning)
touch-probe valid (warning)
6
5*
power down (RAM was initialized) (warning)
overflow of reference counter (warning)
overflow of counter 0, 1 or 2 (warning)
REF reg. valid (warning)
4
3
If a communication collision take place, only the inter-
face with priority (See table 43) executes the write/read
process correctly, but the other interface doesn’t write
any data or read a false value.
2
1
external warning (warning)
0
register comunication collision (warning)
Notes
encoding of bit 9 . . . 0:
0 = message disabled, 1 = message enabled
COMCOL
Addr. 0x49, 0x4A; bit 1
Description
Table 40: Error/Warning Event Masks
Code
0
no communication collision
communication collision
NMASK
Adr 0x03, bit 3:2
1
Bit
1
error/warning event
Notes
reset by reading Adr. 0x49 or 0x4A
AB decodification error. e.g. too high
frequency(error)
Table 37: Communication Collision
0
UPD reg. valid (warning)
Notes
encoding of bit 1...0:
0 = message enabled, 1 = message disabled
Bit TPS signals the actual state of the input pin TPI. If
the pin TPI is high, the bit TPS remains at 1, and if TPI
is set to low, TPS status bit is 0.
Table 41: Error/Warning Event Not Masks
ICHAUS [ IC-HAUS GMBH ]
