iC-MD RS-422 QUADRATURE
ENCODER RECEIVER/COUNTER WITH SPI AND BiSS
Rev A1, Page 19/23
address which is internally increased by 1 following succefully the register. The error in the interface with-
each transmitted byte.
out priority will be signalized by the collision Status bit:
SPICOL or BISSCOL, Adr.0x4A, bit(1:0).
The data length to be read after the read instruction is
variable:
PRIOR
Addr. 0x03; bit 1
Function
0
Code
8 bit
0
1
BiSS priority
For configuration data (Adr.- 0x00 to 0x07), REF and
SPICH (Adr.- 0x10 to 0x25), ROM (Adr.- 0x42, 0x43)
and Status Bit (Adr.- 0x48 to 0x4A). But it is possi-
ble to read several bytes of data consecutively if the
NCS signal is not reset and SCLK continues being
clocked. The address transmitted is then the start ad-
dress which is internally increased by 1 following each
transmitted byte.
SPI priority
Table 43: Interface Priority
SPI Channel: SPI to BiSS communication
The counter register is also used for the transmission
of data from SPI to BiSS. The data exchanging take
place as following:
24+2 bit
For TP1, TP2 and UPD registers.
1. SPI writes the data to be transmitted in address
0x20 to 0x25, this data is written in the counter
registers. The data lenght to be transmitted is
selected by CNTCFG (Table 16) and can be con-
figured as 16, 24, 32 or 48-bit
Variable
For counter data, it depends on the counter configura-
tion CNTCFG (Adr. 0x00 bit (2:0)). See the table 16.
The total length is CNT length + 2 bit (NERR, NWARN)
2. After the writing process, the bit SPICHVAL is set
Interface Priority
to 1 and read via BiSS as Warning bit of channel
The Configuration bit PRIOR (Adr. 0x03, bit 1), set
which interface has priority when taking place a Read-
/Write interface collision. It means that if BiSS and SPI
try to access to the configuration register at the same
time, then only the one with the priority will write/read
0.
3. BiSS reads out the channel 0, the data written
via SPI and two status bits, NERR and NWARN
wich indicates if the read data is valid.
ICHAUS [ IC-HAUS GMBH ]
