iC-MD RS-422 QUADRATURE
ENCODER RECEIVER/COUNTER WITH SPI AND BiSS
Rev A1, Page 20/23
BiSS and SSI INTERFACE
The BiSS interface is a bidirectional serial interface, For a detailed description of the protocol, see the BiSS
which is used to read out the sensor data values and C specification.
to write and read the internal configuration registers.
It consist of 3 configurable channels:
channel
CH0
eata
AB counter
error
NERR
warning
NWARN
data length CRC polynom CRC mode
16 + 2 bit
24 + 2 bit
32 + 2 bit
48 + 2 bit
1000011
inverted
SPI Channel
NERR
NSPICHVAL 16 + 2 bit
24 + 2 bit
1000011
inverted
32 + 2 bit
48 + 2 bit
CH1
CH2
UPD
TP1
TP1
TP2
NABERR NUPDVAL
24 + 2 bit
24 + 2 bit
24 + 2 bit
24 + 2 bit
100101
100101
100101
100101
inverted
inverted
inverted
inverted
NABERR
NABERR
NABERR
NTPVAL
NTPVAL
NTPVAL
Notes
channel 0 data length configurable via:
CNTCFG (Adr.0x00, bit 3:0)
Table 44: BiSS Channels
The error (NERR) and warning (NWARN) bit of the The three channel are enabled by default, but all of
channel 0 signal the same data to be output at the pins them can be disable with the registers NENCH0 (table
NERR and NWARN, it’s by default:
46) and ENCHx (table 47)
NENCH0
Addr. 0x04; bit (2)
0
NERR: ABERR (AB signal error)
Code
Function
0
1
BiSS channel 0 enabled
BiSS channel 0 disabled
NWARN: UPDVAL (UPD Reg. up to date)
This bits can also be configured like the NERR and
NWARN outputs, with the registers MASK (table 40)
and NMASK(table 41)
Table 46: Not Enable BiSS Channel 0
ENCHx
Code
X0
Addr. 0x04; bit (6,4)
Function
00
Two different data can be selected for each chan-
nel, register CHxSEL (table 45) selects the data to be
transmitted by the channels.
BiSS channel 1 disabled
BiSS channel 2 disabled
0X
Table 47: Enable BiSS Channel 1 and 2
CHxSEL
Code
XX0
Addr. 0x04; bit (7,5,3)
Function
000
SSI Protocol
channel 0: AB counter data
channel 0: SPI data channel
channel 1: UPD data
channel 1: TP1 data
An SSI protocol is selected if the input pin SLI is open.
This enable signal has an internal digital filter of 5 µs.
XX1
X0X
X1X
A clock pulse train from a controller is used to gate out
sensor data. Between each clock pulse train there is a
SSI timeout during which fresh data is moved into the
register. Data is shifted out when the iC-MD receives
a pulse train from the controller. When the least sig-
0XX
channel 2: TP1 data
1XX
channel 2: TP2 data
Table 45: BiSS Channel Selection
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