iC-MD RS-422 QUADRATURE
ENCODER RECEIVER/COUNTER WITH SPI AND BiSS
Rev A1, Page 21/23
nificant bit (LSB) goes high after the SSI timeout, new continues being clocked without SSI timeout, it will be
data is available to read.
output a total of 94 bit with the following scheme:
The AB counter data transmitted is in the form of a bi-
nary code (24 bit + NERR + NWARN). If the input MA
Figure 8: Output data with SSI protocol
ACTUATOR OUTPUTS, ERROR and WARNING I/O PINS
The pins NERR and NWARN are low active bidirec- error/warning will be read by the controller via SPI or
tional ports (open collector outputs and digital inputs).
BiSS as status bits.
The inputs are used to latch an external error/warn- The instruction bits ACT0 and ACT1 (tables 25 and 26)
ing (tables 35 and 36) and makes possible that this set the value of the output pins ACT0 and ACT1.
ICHAUS [ IC-HAUS GMBH ]
