iC-GF
TRANSCEIVER
Rev C1, Page 18/26
ttrig
tdead
required – by means of register bit ENPUD (cf. Table
17).
TX
QNx
POL
Adr 0x01; Bit (2)
R/W 0
0
CFI hi → RX hi (ENOD = 0) resp. on (ENOD = 1)
QPx
Pull-down current (ENPUD = 1, INVPUD = 0)
I(QNX)
Iexc()
1
CFI hi → RX lo (ENOD = 0) resp. off (ENOD = 1)
Pull-up current (ENPUD = 1, INVPUD = 0)
Isc()
0
Table 16: Input polarity
0
Isc()
ENPUD
Adr 0x01; Bit (3)
CFI pull-up/down disabled
CFI pull-up/down enabled
R/W 1
0
1
Iexc()
I(QPx)
texc
Table 17: Enable pull-up/down
Figure 9: Dynamic characteristic
The state of the CFI pin (high or low) is mapped inde-
pendent of POL to the register bit IND (see table 18).
Changes at CFI can be logged in the status bit CFED
(and signalled at pin NDIAG), if the bit ENCFD is set to
high. The CFED bit is cleared after read.
Feedback channel CFI–RX configuration
In SPI mode RX is a standard CMOS output, which
can also be configured as an open-drain output, using
the register bit ENOD (cf. Table 15).
IND
0
Adr 0x00; Bit (7)
Input Signal at CFI is low
Input Signal at CFI is high
R
ENOD
Adr 0x01; Bit (0)
Push-pull output
R/W 1
0
1
1
Open-drain output
Table 18: CFI status
Table 15: RX configuration
ENCFD
Adr 0x02; Bit (7)
CFED Disabled
R/W 0
0
1
The polarity of the feedback channel CFI–RX can be
configured using register bit POL (cf. Table 16). Pin
CFP has no function in SPI mode. The POL bit also
controls the pull-up/down current at CFI. The INVPUD
bit changes the polarity of the pull-up/down current at
CFED Enabled
Table 19: Enable edge detection at CFI
CFI independent of the other configurations. The pull- Table 20 summarizes the behaviour of the feedback
up/down current can be disconnected completely – if channel CFI in SPI mode.
Feedback channel CFI
CFI POL INVPUD IND RX (ENOD = 0) RX (ENOD = 1) Current at CFI
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
0
1
1
0
0
1
1
0
off
on
on
off
off
on
on
off
down
down
up
up
up
up
down
down
Table 20: Function table of feedback channel CFI in SPI mode (ENPUD = 1)
Overload detection TYC(1:0), resulting in different overload duty cycles at
In SPI mode the counter decrements of the overload the switching channels. The maximum allowed over-
detection can be programmed with the register DU-
ICHAUS [ IC-HAUS GMBH ]
