iC-GF
TRANSCEIVER
Rev C1, Page 16/26
SPI MODE
TXEN(1:0)
Adr 0x00; Bit (5:4)
R/W 01
In SPI mode the iC-GF is configured and operated us-
ing the on-chip registers. Additionally there is a status
register, where chip events are logged. If any of the
status bits is set to high, the low-active open-drain pin
NDIAG is activated, e.g. for interrupt generation for mi-
cro controllers. The SPI mode is activated when the
pin INV1 is left open and the filter time (cf. Electri-
cal Characteristic No. 614) has elapsed. This enables
communication with the iC-GF via an SPI protocol us-
ing pins MISO, MOSI, SCLK and NCS.
x0
x1
0x
1x
Channel 1 controlled by OUTD(0)
Channel 1 controlled by TX
Channel 2 controlled by OUTD(1)
Channel 2 controlled by TX
Table 6: Transmit enable
OUTD(1:0)
Adr 0x00; Bit (1:0)
R/W 00
x0
x1
0x
1x
Channel 1: push-pull low resp. high/low-side off
Channel 1: push-pull high resp. high/low-side on
Channel 2: push-pull low resp. high/low-side off
Channel 2: push-pull high resp. high/low-side on
Switch enable
There are three different ways of enabling/disabling the
output switches in SPI mode: pin mode, register mode
and mixed mode. In pin mode (TXEN = "11") or reg-
ister mode (TXEN = "00") the OEN pin acts as a com-
mon enable for both switching channels. The OEN reg-
ister on the other hand enables or disables each switch
separately.
Table 7: Output data with INV = "00"
Switch configuration
The configuration of the switches is determined by the
registers QCFG1 and QCFG2; either as high-side, low-
side, push-pull or high impedance (disabled).
Switch enable
OEN pin TXEN(1:0) OEN(1:0) Qx2
Qx1
QCFG1(1:0)
Adr 0x01; Bit (5:4)
disabled
R/W 11
0
1
1
1
X
0
0
0
0
1
1
1
1
00/11
00/11
00/11
XX
XX
01
01
10
10
01
XX
01
10
11
00
0X
1X
X0
X1
01
10
01
10
disabled disabled
disabled enabled
enabled disabled
enabled enabled
disabled disabled
disabled disabled
enabled disabled
disabled disabled
disabled enabled
disabled enabled
enabled disabled
disabled enabled
enabled disabled
00
01
10
11
low-side switch
high-side switch
push-pull
Table 8: Switch configuration Channel 1
QCFG2(1:0)
Adr 0x01; Bit (7:6)
disabled
R/W 11
00
01
10
11
low-side switch
high-side switch
push-pull
01
10
10
Table 9: Switch configuration Channel 2
Table 5: Switch enable, QCFGx = "00"
INV inverts the corresponding switching channel.
INV(1:0)
Adr 0x03; Bit (5:4)
R/W 00
In mixed mode (TXEN = "01" or "10") the OEN pin
acts as an enable only for the channel for which the
TXEN bit is set to "1". The OEN register enables or
disables each switching channel separately. Table 5
summarises these configurations.
x0
x1
0x
1x
Switching channel 1 not inverted
Switching channel 1 inverted
Switching channel 2 not inverted
Switching channel 2 inverted
Table 10: Invert Ouput
Switch control
Each switch can be operated by the OUTD register or
the input pin TX. The register TXEN selects register Table 11 summarises the above configurations for
OUTD or the pin TX for switch control.
channel 1.
A "0" in the register TXEN sets the corresponding
switch to be controlled by the relevant bit of the reg-
ister OUTD.
ICHAUS [ IC-HAUS GMBH ]
