iC-GF
TRANSCEIVER
Rev C1, Page 20/26
V(QX)
Sensor Communication request SCR
OUTD(1:0) QCFG1(1:0) CFI (70...90 µs pulse)
x0
x1
x0
x1
x0
x1
11
11
10
10
01
01
High
Low
High
Low
Low
High
Vtx(CFI)lo
A
B
C
B
A
T
tdnscr max
tdscr(MIN)
tdscr(MAX)
tdnscr min
Table 26: Communication request at channel 1,
OEN = 1, SCR2 = 0, ENSCR = 1, INVx = 0
V(NDIAG)
Figure 11: Communication request timing:
A: Communication request ignored
B: Uncertainty range
C: Communication request acknowl-
edged
SPI INTERFACE
The SPI interface uses the pins NCS, SCLK, MISO and if the NCS signal is not reset and SCLK keeps clock-
MOSI. The protocol is shown in Figures 12 and 13. A ing. The address is internally incremented after each
communication frame consists of one addressing byte transmitted byte. Once the address has reaches the
and one data byte. Bit 7 of the address byte is used last register (0x04), the following 3 increments will read
for selecting a read (set to 1) or a write (set to 0) oper- and write dummy data. After that addressing will start
ation. The other bits are used for register addressing. again at 0x00. The required timing for the SPI signals
It is possible to transmit several bytes consecutively, during a communication is shown in Figure 1.
Polarity 0, Phase 0
NCS
SCLK
ADR(6:0)
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
X
MOSI
MISO
High Impedance
Figure 12: SPI write data
Polarity 0, Phase 0
NCS
SCLK
MOSI
MISO
don't care
ADDRESS(6:0)
High Impedance
n
n-1
n-2
n-3
n-4
n-5
5
4
3
2
1
0
X
High Impedance
Figure 13: SPI read data
ICHAUS [ IC-HAUS GMBH ]
