IBMN312164CT3
IBMN312404CT3
IBMN312804CT3
128Mb Synchronous DRAM - Die Revision B
Preliminary
Operating, Standby, and Refresh Currents (T = 0 to +70°C, V = 3.3V ±0.3V)
A
DD
Speed
Parameter
Symbol
Test Condition
Units Notes
-75H -75D -75A
-260
80
-360
80
-10
65
1 bank operation
tRC = tRC(min), tCK = min
Active-Precharge command
Operating Current
ICC1
90
90
85
mA
1, 2, 3
cycling without burst operation
CKE £ VIL(max), tCK = min,
CS = VIH(min)
ICC2P
ICC2PS
ICC2N
2
2
2
2
2
2
2
2
2
2
2
2
mA
mA
1
1
Precharge Standby Current
in Power Down Mode
CKE £ VIL(max), tCK = Infinity,
CS = VIH(min)
CKE ³ VIH(min), tCK = min,
CS = VIH (min)
50
9
50
9
45
9
35
9
35
9
35
9
mA
mA
mA
mA
1, 5
1, 7
1, 5
1, 6
Precharge Standby Current
in Non-Power Down Mode
ICC2NS CKE ³ VIH(min), tCK = Infinity,
CKE ³ VIH(min), tCK = min,
CS = VIH (min)
ICC3N
60
9
60
9
50
9
40
9
40
9
40
9
No Operating Current
(Active state: 4 bank)
ICC3P CKE £ VIL(max), tCK = min,
tCK = min,
Read/ Write command cycling,
Multiple banks active, gapless
Operating Current (Burst
Mode)
ICC4
135
135
120
90
90
90
mA
1, 3, 4
data, BL = 4
tCK = min, tRC = tRC(min)
CBR command cycling
Auto (CBR) Refresh Current ICC5
Self Refresh Current ICC6
190
2
190
2
190
2
170
2
170
2
145
2
mA
mA
1
1
CKE £ 0.2V
1. Currents given are valid for a single device. The total current for a stacked device depends on the operation being performed on the
other deck.
2. These parameters depend on the cycle rate and are measured with the cycle determined by the minimum value of tCK and tRC. Input
signals are changed up to three times during tRC(min).
3. The specified values are obtained with the output open.
4. Input signals are changed once during tCK(min).
5. Input signals are changed once during three clock cycles.
6. Active Standby Current will be higher if Clock Suspend is entered during a burst read cycle (add 1mA per DQ).
7. Input signals are stable.
©IBM Corporation. All rights reserved.
06K7582.H03335A
01/01
Use is further subject to the provisions at the end of this document.
Page 36 of 66
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