IBMN312164CT3
IBMN312804CT3
IBMN312404CT3
Preliminary
128Mb Synchronous DRAM - Die Revision B
Read Cycle
-75H
-75D
-75A
-260
-360
-10
Symbol
Parameter
Units Notes
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
—
2.7
0
—
—
—
2.7
0
—
—
—
2.7
0
—
—
—
5.4
—
—
2.5
3
—
—
—
6
2.5
3
—
—
—
6
3
3
0
3
3
2
—
—
—
7
ns
ns
ns
ns
ns
CK
1
tOH Data Out Hold Time
tLZ Data Out to Low Impedance Time
2, 4
—
—
0
0
tHZ3 Data Out to High Impedance Time
tHZ2 Data Out to High Impedance Time
tDQZ DQM Data Out Disable Latency
3
5.4
5.4
—
3
5.4
—
3
3
3
3
3
3
—
2
—
2
3
6
3
8
8
2
—
2
—
2
—
—
1. AC Output Load Circuit A.
2. AC Output Load Circuit B.
3. Referenced to the time at which the output achieves the open circuit condition, not to output voltage levels.
4. Data Out Hold Time with no load must meet 1.8ns (-75H, -75D, -75A).
Refresh Cycle
-75H
-75D
-75A
-260
-360
-10
Symbol
Parameter
Units Notes
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
tREF Refresh Period
—
10
64
—
—
10
64
—
—
10
64
—
—
10
70
64
—
—
10
70
64
—
—
10
84
64
—
ms
ns
ns
1
2
tSREX Self Refresh Exit Time
tRFC Bank Cycle Time (Auto Refresh)
67.5
67.5
67.5
1. 8192 auto refresh cycles.
2. These parameters account for the number of clock cycles and depend on the operating frequency of the clock, as follows; the num-
ber of clock cycles = specified value of timing/clock period (count fractions as a whole number).
Write Cycle
-75H
-75D
-75A
-260
-360
-10
Symbol
Parameter
Units
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
tDS
tDH
Data In Set-up Time
Data In Hold Time
1.5
0.8
15
—
—
—
1.5
0.8
15
—
—
—
1.5
0.8
15
—
—
—
2
1
—
—
—
2
1
—
—
—
3
1
—
—
—
ns
ns
ns
tDPL Data input to Precharge
20
20
20
Data In to Active Delay
tDAL3
5
—
5
—
5
—
5
—
5
—
5
—
CK
CAS Latency = 3
Data In to Active Delay
tDAL2
5
0
—
—
—
0
—
—
—
0
—
—
5
0
—
—
5
0
—
—
3
0
—
—
CK
CK
CAS Latency = 2
tDQW DQM Write Mask Latency
©IBM Corporation. All rights reserved.
06K7582.H03335A
01/01
Use is further subject to the provisions at the end of this document.
Page 39 of 66
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