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IBMN312404CT3B-75H 参数 Datasheet PDF下载

IBMN312404CT3B-75H图片预览
型号: IBMN312404CT3B-75H
PDF下载: 下载PDF文件 查看货源
内容描述: [Synchronous DRAM, 32MX4, 5.4ns, CMOS, PDSO54, 0.400 INCH, PLASTIC, TSOP2-54]
分类和应用: 时钟动态存储器光电二极管内存集成电路
文件页数/大小: 66 页 / 2855 K
品牌: IBM [ IBM ]
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IBMN312164CT3  
IBMN312404CT3  
IBMN312804CT3  
128Mb Synchronous DRAM - Die Revision B  
Preliminary  
Current State Truth Table (Part 2 of 3)(See note 1)  
Command  
Current State  
Action  
Notes  
CS RAS CAS WE BS0,BS1  
A11 - A0  
Description  
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
H
L
OP Code  
Mode Register Set  
ILLEGAL  
X
BS  
BS  
BS  
BS  
X
X
X
Auto or Self Refresh ILLEGAL  
L
H
H
L
Precharge  
ILLEGAL  
ILLEGAL  
ILLEGAL  
ILLEGAL  
4
4
4
4
Read with  
Auto Pre-  
charge  
L
H
L
Row Address Bank Activate  
H
H
H
X
L
Column  
Write  
L
H
H
X
L
Column  
Read  
H
X
L
X
X
No Operation  
Device Deselect  
Mode Register Set  
Continue the Burst  
Continue the Burst  
ILLEGAL  
X
OP Code  
L
L
H
L
X
BS  
BS  
BS  
BS  
X
X
X
Auto or Self Refresh ILLEGAL  
L
H
H
L
Precharge  
ILLEGAL  
4
4
4
4
Write with  
Auto Pre-  
charge  
L
H
L
Row Address Bank Activate  
ILLEGAL  
H
H
H
X
L
Column  
Write  
ILLEGAL  
L
H
H
X
L
Column  
Read  
ILLEGAL  
H
X
L
X
X
No Operation  
Device Deselect  
Mode Register Set  
Continue the Burst  
Continue the Burst  
ILLEGAL  
X
OP Code  
L
L
H
L
X
BS  
BS  
BS  
BS  
X
X
X
Auto or Self Refresh ILLEGAL  
Precharge No Operation; Bank(s) idle after tRP  
L
H
H
L
L
H
L
Row Address Bank Activate  
ILLEGAL  
ILLEGAL  
ILLEGAL  
4
4
4
Precharging  
H
H
H
X
L
Column  
Write  
L
H
H
X
L
Column  
Read  
H
X
L
X
X
No Operation  
Device Deselect  
Mode Register Set  
No Operation; Bank(s) idle after tRP  
No Operation; Bank(s) idle after tRP  
ILLEGAL  
X
OP Code  
L
L
H
L
X
BS  
BS  
BS  
BS  
X
X
X
Auto or Self Refresh ILLEGAL  
L
H
H
L
Precharge  
ILLEGAL  
4
4, 10  
4
L
H
L
Row Address Bank Activate  
ILLEGAL  
Row  
Activating  
H
H
H
X
Column  
Write  
ILLEGAL  
L
H
H
X
Column  
Read  
ILLEGAL  
4
H
X
X
X
No Operation  
Device Deselect  
No Operation; Row Active after tRCD  
No Operation; Row Active after tRCD  
X
1. CKE is assumed to be active (high) in the previous cycle for all entries. The Current State is the state of the bank that the Com-  
mand is being applied to.  
2. All Banks must be idle; otherwise, it is an illegal action.  
3. If CKE is active (high) the SDRAM will start the Auto (CBR) Refresh operation, if CKE is inactive (low) than the Self Refresh mode  
is entered.  
4. The Current State refers to only one of the banks. If BS selects this bank then the action is illegal. If BS selects the bank not being  
referenced by the Current State then the action may be legal depending on the state of that bank.  
5. If CKE is inactive (low) then the Power Down mode is entered; otherwise there is a No Operation.  
6. The minimum and maximum Active time (tRAS) must be satisfied.  
7. The RAS to CAS Delay (tRCD) must occur before the command is given.  
8. Column address A10 is used to determine if the Auto Precharge function is activated.  
9. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements.  
10. The command is illegal if the minimum bank to bank delay time (tRRD) is not satisfied.  
©IBM Corporation. All rights reserved.  
06K7582.H03335A  
01/01  
Use is further subject to the provisions at the end of this document.  
Page 32 of 66  
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