IBMN312164CT3
IBMN312404CT3
IBMN312804CT3
128Mb Synchronous DRAM - Die Revision B
Preliminary
Clock Frequency and Latency
Symbol
fCK
Parameter
Clock Frequency
-75H
133
7.5
2
-75D
133
7.5
3
-75A
133
7.5
3
-260
100
-360
100
-10
Units
100
10
2
66
15
2
100
10
3
71
MHz
ns
tCK
Clock Cycle Time
10
3
2
2
7
7
5
2
5
2
1
0
0
2
1
10
3
2
2
7
7
5
2
5
2
1
0
0
2
1
14
2
1
2
5
5
4
2
3
2
1
0
0
2
1
tAA
CAS Latency
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
tRP
Precharge Time
2
2
3
2
2
3
tRCD
tRC
RAS to CAS Delay
2
2
3
2
2
3
Bank Cycle Time
8
8
9
7
6
9
tRFC
tRAS
tDPL
tDAL
tRRD
tCCD
tWL
Bank Cycle Time (Auto Refresh)
Minimum Bank Active Time
Data In to Precharge
Data In to Active/Refresh
Bank to Bank Delay Time
CAS to CAS Delay Time
Write Latency
9
9
9
7
6
9
6
6
6
5
4
6
2
2
2
2
2
2
5
5
5
5
5
5
2
2
2
2
2
2
1
1
1
1
1
1
0
0
0
0
0
0
tDQW
tDQZ
tCSL
DQM Write Mask Latency
DQM Data Disable Latency
Clock Suspend Latency
0
0
0
0
0
0
2
2
2
2
2
2
1
1
1
1
1
1
©IBM Corporation. All rights reserved.
06K7582.H03335A
01/01
Use is further subject to the provisions at the end of this document.
Page 40 of 66
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