IBM3229P2035
Advance
IBM Packet Routing Switch Serial Interface Converter
Table 2: Egress I/O Pin Description
Pin Name
Type
Function
Transmit clock (PE_TXCLK_OUT clock) is issued from two clock domains:
At POR it is connected to the microprocessor clock until the POR is completed.
Generated after POR completion by either the smooth PLL clock out (derived from either
SWITCH_PLL X or Y), or by an externally provided clock (for example the PE clock that ranges from
50 - 125 MHz).
PE_TXCLK_OUT
Output
PE_TXCLK_OUT source is selected according to the programming of the
“PE_TXCLK_OUT_source_l[1:0]” bits as given in the configuration table registers.
Transmit Data is transferred from the converter to the PE on a 32-bits word basis. TXDATA[31] is the
MSB, TXDATA[0] is the LSB.
TXDATA[31:0]
Output
Output
Transmit Data Parity bit serves as odd parity bit over the 32 TXDATA bits. Parity generation mode is
enabled/disabled by the TXPRTY_enb_l bit in the configuration table registers.
TXPRTY (Output)
These are the same signal, but can have two names.
Transmit Packet Available/TXFULL is asserted by the PE device when it is ready to receive at least
one complete packet. During a packet transfer, the PE device has at least four cycles before the end
of the current packet transfer to assert TXPAV if it can accept immediate transfer of the subsequent
packet, or to de-assert TXPAV if it cannot.
TXPAV
TxFULL
Input
Once the converter detects TXPAV de-asserted, it may only transmit four more 32-bits data words to
the PE device. It is recommended that the PE device keeps TXPAV signal asserted until four cycles
before the end of the packet transfer.
TXPAV and TXFULL lines have the same timing.
TXPAV asserted is equivalent to TXFULL de-asserted.
Transmit Start Of Packet is asserted for one clock cycle by the converter when it starts a packet trans-
fer to indicate the first available 32-bits data word of the packet.
TXSOP
TXENB
Output
Output
The converter asserts Transmit Enable to indicate that valid 32-bits data words are on the bus. When
TXPAV is asserted during a packet transfer (at least four clock cycles before the end of the current
packet transfer), the converter indicates one clock cycle after the last word of the current packet if it is
(TXENB asserted) or is not (TXENB de-asserted) ready to send a new complete packet.
When TXPAV is de-asserted during a packet transfer (at least four clock cycles before the end of the
current packet transfer) TXENB is de-asserted four clock cycles afterwords to stop the transfer.
prssi.02.fm
Functional Description
Page 25 of 154
March 1, 2001
IBM [ IBM ]
