IBM3229P2035
IBM Packet Routing Switch Serial Interface Converter
Advance
3.2.2 Egress Interface
3.2.2.1 Bus Protocol
The egress block is the transmit path between the IBM Packet Routing Switch Serial Interface Converter (the
converter) and the protocol engine (PE). The converter sends data according to the following protocol:
• The converter provides the transmit clock called PE_TXCLK_OUT
• The PE asserts the TXPAV signal when it is ready to receive at least one packet from the converter
• When the converter is ready to send at least one packet on the bus and the PE device has asserted the
signal TXPAV, it starts the transfer by simultaneously asserting the signal TXSOP and TXENB
• TXDATA[31:0] is transferred on each low-to-high clock transition, the first data word of the packet being
transferred simultaneously with the signal TXSOP
• The PE device de-asserts the TXPAV signal at least four cycles before the end of the current packet
transfer to indicate that it cannot accept an immediate transfer of the subsequent packet
This protocol applies when a user wishes to use OBFC mechanisms in addition to IBFC if the attached PE
has two sets of buffers. The small buffer allows the link layer to absorb the lack of synchronization between
the UTOPIA-3 interface and the rest of the PE chip. The large buffer absorbs traffic burst. Under pure IBFC
operation, because all the flow control is performed in band (through the packet header), there is no need for
the use of TXENB / TXFULL (TXPAV) protocols. Also under IBFC, if there is no data packet to be sent by the
converter, it will insert an idle packet that will be discarded by the PE.
Functional Description
Page 24 of 154
prssi.02.fm
March 1, 2001
IBM [ IBM ]
