IBM3229P2035
Advance
IBM Packet Routing Switch Serial Interface Converter
Table 1: Ingress I/O Pin Description
Pin Name
Function
Receive Clock (PE_RXCLK_OUT clock) is issued from two clock domains:
At POR it is connected to the microprocessor clock until the POR completes.
After POR completes, it is generated by either the smooth PLL clock out (derived from SWITCH_PLL X or
Y) or by an externally provided clock (for example the 50 - 125 MHz PE clock).
PE_RXCLK_OUT (Output)
PE_RXCLK_OUT source is selected according to the programming of the
“PE_RXCLK_OUT_source_l[1:0]” bits in the configuration table registers.
Receive Data is transferred from the PE device to the converter on a 32-bits word basis.
RXDATA[31:0] (Input)
RXPRTY (Input)
LSB
MSB
RXDATA[0]RXDATA[31]
Receive Data Parity Bit is the odd parity bit over the 32 RXDATA bits. The parity_check mode is enabled/
disabled by the RXPRTY_enb_l bit in the configuration table registers.
PE device asserts Receive Packet Available when at least one complete packet is ready to be transmitted
on the bus. The signal remains asserted during the current packet transfer (packet level handshake) and
indicates, in the cycle following the last word of the current packet, if there is (RXPAV asserted) or is not
(RXPAV de-asserted) a new packet to transfer.
RXPAV (Input, active high)
RXSOP (Input, active high)
RXPAV must be asserted when operating in IBFC mode.
PE device asserts Receive Start of Packet for one clock cycle when it starts a packet transfer to indicate
the packet’s first 32-bits data word.
The converter asserts Receive Enable to indicate its readiness to receive at least one complete packet.
The signal remains asserted during the transfer of the current packet (packet level handshake) and, two
RXENB (Output, active low) cycles before the end of the current packet transfer, indicates whether it is (RXENB asserted) or is not
(RXENB de-asserted) ready to receive a new complete packet. As this signal is pipelined, the PC devices
will respond at least two clock cycles after the RXENB is asserted or de-asserted
3.2.1.2 Ingress Operation and Timing
Figure 5: Ingress Timing for RXENB Deasserted by Converter for 1 Clock Cycle
Ingress Operation for 64-Byte Packet Flow Control
T0
T2
T4
T6
T8
T10
T12
T14
T16
T18
T20
T22
T24
PE_RXCLK_OUT
RXDATA[31:0]
RXSOP
NOP NOP NOP H1 H2 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 NOP H1 H2 W1 W2 W3
RXPAV
RXENB
1 wait state
Converter cannot accept
a new packet
Converter can again
accept a new packet
prssi.02.fm
March 1, 2001
Functional Description
Page 21 of 154
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