IBM3229P2035
Advance
IBM Packet Routing Switch Serial Interface Converter
3.3 Packet Reshuffling
3.3.1 Ingress Receive Logical Unit Framing
The Ingress LU formatter is the interface between the PE interface logic and the ingress FIFO (RXFIFO)
which translates various types of ingress packet formats into the IBM 28.4 G Packet Routing Switch (switch)
LU format is defined in the IBM Packet Routing Switch Serial Interface Converter (the converter) configura-
tion registers.
Data inputs are in a 4-byte format. The ingress LU formatter extracts TxPause flow control information from
the incoming packet qualifier byte. The incoming packet is comprised of 16 to 20 32-bit words. Packet
Reshuffling stores the packet in the switch format in four LUs which, when fully generated, are forwarded to
the RXFIFO.
The Ingress LU Formatter:
• Discard idle packets
• Extract Send Grant flow control information from the incoming PQ byte
• Modify the packet qualifier byte into switch format and compute the associated parity
• Change the position of the bit map bytes in the packet header
• Know of any bus parity error through the PE interface RXPRTY_error
• May not forward a packet to the RXFIFOs in case of any bus or header error (depending upon a configu-
ration register setting)
3.3.1.1 Header Bytes Reshuffling
The header bytes are moved according to the content of the "byte positioning in LU formatter" configuration
fields. These allow any byte contained in the four words to be moved to any other byte position in the master
LU.
3.3.1.2 Input/Output Packet Format
The following tables highlight the position of the different information fields in an incoming packet. All bytes in
the first four words can be repositioned in the switch header according to the formatter field in the configura-
tion registers. The data source is based on a word/byte coordinate in a nibble. The first two bits correspond to
the word selection; the last two bits correspond to the byte selection.
Example of Header Bytes in Sequence
Byte
Byte 0
Byte 1
Byte 2
Byte 3
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Word 0 Packet Qualifier
Word 1 BM[7:0] BM4
Word 2
BM[31:24] BM1
BM[23:16] BM2
BM[15:8] BM3
Word 15
prssi.02.fm
Functional Description
Page 27 of 154
March 1, 2001
IBM [ IBM ]
