IBM3229P2035
IBM Packet Routing Switch Serial Interface Converter
Advance
3.2.2.2 Egress Operation and Timing
Figure 10: TXFULL Timing
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17
CLK
TXDATA[31:0]
DATA PKT
DATA PKT
DATA PKT
DATA PKT
28 CLK CYCLES
28 CLK CYCLES
DATA PKT
1 PKT ~
1 PKT ~
DATA PKT
DATA PKT
DATA PKT
DATA PKT
DATA PKT
TXFULL
TXDATA[31:0]
DATA PKT
1 PKT ~
1 PKT ~
DATA PKT
TXFULL Cycle
TXFULL Cycle
Ignored
Figure 11: Egress Timing for Back-to-Back Packets
Transmit Operation for 64-Byte Back-t0-Back Packet Transmission
T0
T2
T4
T6
T8
T10
T12
T14
T16
T18
T20
T22
T24
PE_TXCLK_OUT
TXDATA[31:0]
TXSOP
NOP NOP NOP H1 H2 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 H1 H2 W1 W2 W3 W4
TXPAV
TXENB
1
2
3
4
Protocol engine ready
to accept a new packet
Converter keeps
TXENB asserted
3.2.3 TXFULL Timing
When the PE asserts TXFULL to stop the flow of packets, its effect is extended for 28 PE clock cycles from
the end of the current packet. After the first packet following the deassertion of TXFULL by the PE, the
UDASL inserts two empty slots of idle (no data) before the traffic resumes. If the PE resasserts TXFULL upon
the reception of the first packet during the TXFULL cycle, it will be ignored until the end of the complete cycle.
Functional Description
Page 26 of 154
prssi.02.fm
March 1, 2001
IBM [ IBM ]
