IBM3229P2035
IBM Packet Routing Switch Serial Interface Converter
Advance
Table 20: Tests Signals
Input/
Output
Name
CE1_C2
CE0_IO
Levels
Description
Notes
External source of the internal SRL scan C clock used during LSSD test to
enable the tester to independently source the internal SRL clocks from the
primary inputs (used for RAMS).
Input
LVCMOS
LVCMOS
1
1
Used to force the JTAG EXTEST operation for IBM test methodology pur-
poses.
Input
CE0_Scan
CE0_TEST
Input
Input
LVCMOS
LVCMOS
Gates both the A and B LSSD test clocks.
1
1
Forces "0" in system mode and ‘1’ in LSSD test mode.
External source of the internal GRA scan C clock used during LSSD test to
enable the tester to independently source the internal GRA clocks from the
primary inputs.
TEST_C3
Input
LVTTL
1
Programs the PLL to perform parametric testing at the wafer and module
level.
PE_TESTIN
Input
Input
LVCMOS
LVCMOS
LVCMOS
2
2
2
Programs the DASL PLL for fabric X to perform parametric testing at the
wafer and module levels.
SWITCH_X_TESTIN
Programs the DASL PLL for fabric Y to perform parametric testing at the
wafer and module levels.
SWITCH_Y_TESTIN
PE_TESTOUT
Input
Output
LVCMOS
LVCMOS
LVCMOS
Monitor TESTOUT output during PLL test to verify the PLL output frequency.
Monitor TESTOUT output during PLL test to verify the PLL output frequency.
Monitor TESTOUT output during PLL test to verify the PLL output frequency.
SWITCH_X_TESTOUT Output
SWITCH_Y_TESTOUT Output
Connected to the ABIST controller STCLK input and used only during test
operation. Keep this signal inactive (tied to ground) during system mode to
reduce power consumption in the BIST logic.
ABIST_CLK
Input
LVCMOS
LVTTL
Each SRAM DIAGOUT output is multiplexed to this ABIST_DIAGOUT PO to
observe the pass/fail flag of individual arrays during the ABIST diagnostic
mode. See register @8C bit 2 for X or Y result on that pin.
ABIST_DIAGOUT
Output
1. An internal pull-up resistor forces the inactive state.
2. Must be kept LOW during normal PLL operation.
Table 21: JTAG Interface External Signals
Input/Out-
Name
Levels
Description
Notes
put
Input
Input
Input
Output
TCK
TMS
TDI
3.3 V LVTTL receiver tri-state CIO Test Clock Input
3.3 V LVTTL receiver tri-state CIO Test Mode Select Input
3.3 V LVTTL receiver tri-state CIO Test Data Input
3.3 V LVTTL 50 Ω tri-state CIO Test Data Output
1, 2
1, 2
1, 2
1, 2
TDO
Test Reset Input must be asserted during the power-on-reset to
reset the JTAG control logic.
TRST
Input
3.3 V LVTTL receiver tri-state CIO
1, 2
1. An internal pull-up resistor forces the inactive state
2. . See IEEE 1149.1 specification for details.
I/O Definition and Package Pin Assignment
Page 112 of 154
prssi.02.fm
March 1, 2001
IBM [ IBM ]
