IBM3229P2035
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IBM Packet Routing Switch Serial Interface Converter
6. JTAG Description
The IBM Packet Routing Switch Serial Interface (the converter) is compliant with the IEEE Standard Test
Access Port and Boundary-Scan Architecture for testing and debugging components assembled at the board
level. (See "IEEE Standard Test Access Port and Boundary-Scan Architecture", doc. IEEE Std 1149.1-1990,
and the IBM ASIC Products Application Note "IEEE 1149.1 Boundary-Scan in IBM ASICs", 11/97, version 4.)
JTAG test architecture consists of a Test Access Port (TAP) and associated controller, an Instruction
Register, and (on the converter) three Test Data Registers named the Bypass Register, the Idcode Register,
and the Boundary Scan Register.
The TAP, a general-purpose port, provides access to the implemented test support functions defined by the
JTAG Standard. It consists of the following five ports: the Test Clock Input (TCK), the Test Mode Select Input
(TMS), the Test Data Input (TDI), the Test ReSeT input (TRST), and the Test Data Output (TDO). The TAP
controller is a synchronous finite state machine that responds to changes at the TMS and TCK signals and
controls the sequence of operations of the internal test logic. It generates the clock and control signals
required to shift data down the Instruction Register and Test Data Registers. These registers constitute sepa-
rate shift-register based paths that are connected in parallel between the TDI and TDO.
The Instruction Register is three bits long. It captures the Instruction Opcode desired during a test. The
converter supports the following instructions declared in the JTAG Standard: EXTEST, INTEST, SAMPLE,
IDCODE, HIGHZ, CLAMP and BYPASS.
Table 17: Supported JTAG Instructions
Instruction Name
Extest
Instruction Opcode
000
001
010
011
100
110
111
Intest
Sample
IDcode
Hi-Z
Clamp
Bypass
The Bypass Register is a one bit long shift register and is scannable during the BYPASS instruction. It
provides a minimum length serial path to move test data between TDI and TDO. Use the Bypass Register to
speed access to JTAG registers in other components on a board-level test data path.
The Boundary Scan Register is a shift register that allows sampling and/or forcing of signals flowing into and
out of the system logic through the system ports.
During the JTAG operation the following converter PIs must be at the specific value indicated in the following
table. As these PIs are already internally tied up or tied down, they do not need any user force action except
the RI line, which must be forced to 1 externally.
prssi.02.fm
JTAG Description
Page 109 of 154
March 1, 2001
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