IBM3229P2035
Advance
IBM Packet Routing Switch Serial Interface Converter
7. I/O Definition and Package Pin Assignment
7.1 Signals Description
All functional signals are 3.3 V LVTTL compatible for drivers and receivers except the following:
• Protocol engine interface
• Protocol engine clocks provided by the IBM Packet Routing Switch Serial Interface Converter
• Back pressure serial link
• LSDD and JTAG test signals
These are based on the tri-state driver/receiver (BP2550 type) that interfaces 2.5 V internal functions with 3.3
V-tolerant 2.5 V CMOS drivers and receivers off chip bidirectional data buses. The driver is 50 Ω source-
terminated.
The switch fabric clocks are balanced HSTL levels.
Table 20: Tests Signals
Input/
Output
Name
DI1
Levels
Description
Notes
Non-test driver inhibit for all chip boundary outputs.
0
1
Chip boundary outputs are disabled and in tri-state.
Inactive, all boundary outputs are controlled by normal functions. An
internal pull-up resistor forces the inactive state.
LVCMOS
Boundary outputs are chip outputs or common I/O's that serve as primary
outputs of the internal boundary logic. Feed directly by boundary latches or
special boundary logic books that make up the boundary logic.
The test driver inhibit for all chip non-boundary outputs.
0
Chip non-boundary outputs are disabled and in tri-state. An internal
pull-up resistor forces the inactive state.
DI2
RI
Input
Input
LVCMOS
LVCMOS
1
Inactive, all non-boundary outputs are controlled by normal func-
tions.
Non-boundary outputs are chip outputs or common I/O's that bring test func-
tion and LSSD scan data directly to and from the internal boundary logic.
Gates all boundary receivers during internal test to prevent unknown states
from entering the internal logic and to reduce switching activities. RI pad
must be tied up externally for system mode. When active, all boundary
receivers are placed in a known state independent of the receiver input.
External source of the internal SRL scan A clock used during LSSD test to
enable the tester to independently source the internal SRL clocks from the
primary inputs.
CE1_A
CE1_B
Input
Input
Input
Input
LVCMOS
LVCMOS
LVTTL
1
1
1
1
External source of the internal SRL scan B clock used during LSSD test to
enable the tester to independently source the internal SRL clocks from the
primary inputs.
External source of the internal SRL scan B clock used during LSSD test to
enable the tester to independently source the internal SRL clocks from the
primary inputs.
TEST_B2
CE1_C1
External source of the internal SRL scan C clock used during LSSD test to
enable the tester to independently source the internal SRL clocks from the
primary inputs (used for logic).
LVCMOS
1. An internal pull-up resistor forces the inactive state.
2. Must be kept LOW during normal PLL operation.
prssi.02.fm
I/O Definition and Package Pin Assignment
Page 111 of 154
March 1, 2001
IBM [ IBM ]
