IBM3229P2035
IBM Packet Routing Switch Serial Interface Converter
Advance
5. IBM Packet Routing Switch Serial Interface Converter Latency
There are two kinds of flow control latencies to be considered: packet latency and flow control latency.
Packet latency is shown below. Packet reshuffling is the main cause because, on ingress, the entire packet
must be received before it can be ascertained if the packet must be discarded due to errors. The re-synchro-
nization layer between the PE clock domain and the switch clock domain is the secondary contributor to
packet latency.
Figure 33: Converter Latency Diagram
Protocol Engine
Interface
Interfacing
Packet Reshuffling
Packet Buffering
DASL Ports
2cc
DASL Macro
IBM 28.4 G
Packet Routing
Switch
1cc
1p
1+3cc
3cc
RX_Enable
Elements
X Plane
Ingress DASL
Interface:
Synch/Idle/Yellow
LU Serializer
CRC Insert
Receive DASL
Interface - X
Ingress
Ingress PE
Interface
X RX FIFO
LU Framing
Parity Checking
Shared Memory Grant-X
Grant Control
Generation
Force SMG0=0
Protocol
Engine
O
Output Queue Grant
32-bits
125 MHz
Interface
Egress DASL
Interface
Header Extraction
LU Deserializer
CRC Check
TX Framing
Header Handling
Idle Generation
Egress PE
Interface
Transmit DASL
Interface - X
X TX FIFO
MUX
Send Grant_X
TXFULL
Egress
Flow Control
1cc
1p
1+3cc
1p +1cc
4 to 7cc
cc : clock cycle
p: packet cycle
Flow control information latency has two impacts:
• The shared memory thresholds within the switch have to be set to low sharing (for example: Priority 3 to
16 Packets, Priority 2 to 32 packets, Priority 1 to 48 packets, and Priority 0 to 64 packets).
• The flow control check bit 10 of mode register must be disabled.
IBM Packet Routing Switch Serial Interface Converter Latency
Page 108 of 154
prssi.02.fm
March 1, 2001
IBM [ IBM ]
