IBM3009K2672
IBM SONET/SDH Framer
C at outputs: 5 pF - 40 pF
L
Symbol
Parameter
GPPCLK clock period (not shown in diagram)
GPPCLK duty cycle
Min
20
Typ
Max
60
Unit
ns
Notes
1
tCYC
tPWH / tCYC
40
%
GPADDR(13:0)/GPR/W set-up time to GPSEL asser-
tion
tSU1
tH1
tSU2
tD1
0
ns
ns
GPADDR(13:0)/GPR/W hold time from GPSEL de-
assertion
0
GPSEL assertion set-up time to GPDS assertion
GPSEL assertion to GPDTACK valid delay
-6.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
16
16
tD2
GPSEL de-assertion to GPDTACK tri-state delay
GPSEL de-assertion (high) time between accesses
GPSEL hold time from GPDS de-assertion
4.0
2
tINACTIVE
tH2
tCYC
0
tH3
GPDS hold time from GPDTACK assertion
10
tD3
GPDATA(7:0) input valid delay from GPDS assertion
GPDATA(7:0) input valid hold from GPDS de-assertion
GPDTACK assertion from GPDS assertion
20
tH4
0
tDELAY
tCYC
tDELAY(max)
3
1. A clock still needs to be applied to the GPPCLK clock pin of the SONET/SDH framer even if an asynchronous microprocessor
interface is used.
2. There might be a de-asserted (high) phase of GPDTACK before turning tri-state if GPDS is de-asserted early.
3. tDELAY(max) = 7 x tCYC + 6 x tmin where tmin is the cycle time of the lowest-frequency chiplet clock. The lowest frequency of the
chiplet clocks is the lower of 6.48 MHz or the UTOPIA interface clock frequencies.
Timing Characteristics
Page 76 of 279
ssframer.01
8/27/99
IBM [ IBM ]
