IBM3009K2672
IBM SONET/SDH Framer
C at outputs: 5 pF - 40 pF
L
Symbol
Parameter
Min
20
40
0
Typ
Max
60
Unit
ns
%
Notes
1
tCYC
tPWH / tCYC
tSU1
GPPCLK clock period (not shown in diagram)
GPPCLK duty cycle
GPADDR/GPR/W set-up time to GPSEL assertion
GPADDR/GPR/W hold time from GPSEL de-assertion
GPSEL assertion set-up time to GPDS assertion
GPSEL assertion to GPDTACK valid delay
GPSEL de-assertion to GPDTACK tri-state delay
GPSEL de-assertion (high) time between accesses
GPSEL hold time from GPDS de-assertion
GPDS hold time from GPDTACK assertion
GPDTACK assertion from GPDS assertion
ns
ns
ns
ns
ns
ns
ns
ns
ns
tH1
0
tSU2
-6.0
tD1
16
16
tD2
4.0
2
3
tINACTIVE
tH2
tCYC
0
tH3
10
tDELAY
tCYC
tDELAY(max)
15
GPDATA(7:0) output valid delay from
GPDTACK assertion
tD4
ns
GPDATA(7:0) output valid hold from GPDS
de-assertion
tH5
tH6
tD5
tr, tf
4.0
3.0
ns
ns
ns
ns
GPDATA output valid hold from GPSEL de-assertion
GPDATA(7:0) output tri-state delay from GPDS/GPSEL
de-assertion
17
GPDATA(7:0) output rise and fall times
0.8
8.5
1. A clock still needs to be applied to the GPPCLK clock pin of the SONET/SDH framer even if an asynchronous microprocessor
interface is used.
2. There might be a de-asserted (high) phase of GPDTACK before turning tri-state if GPDS is de-asserted early.
3. tDELAY(max) = 7 x tCYC + 6 x tmin where tmin is the cycle time of the lowest-frequency chiplet clock.
The lowest frequency of the chiplet clocks is the lower of 6.48 MHz or the UTOPIA interface clock frequencies.
Timing Characteristics
Page 78 of 279
ssframer.01
8/27/99
IBM [ IBM ]
