IBM3009K2672
IBM SONET/SDH Framer
The transmit Telecom Bus failure input (TXTB#FAIL) is generated by the transmit Telecom Bus device to the
SONET/SDH framer to tell the SONET/SDH framer to generate AIS-P in the STM-1/STS-3c for which the
alarm occurs, regardless of whether retiming is turned on or off. This pin has an internal pull-up resistor to
allow automatic AIS generation if a board failure occurs. If this pin is not used it should be tied to ground. It
should be noted that when an STM-4c/STS-12c payload is being processed, so that the four transmit Tele-
com Bus interfaces act as a single 32-bit wide interface, that all four TXTB#FAIL inputs must be activated
simultaneously.
Receive Telecom Bus
There are four receive Telecom Bus interfaces, numbered 1-4, allowing the back-to-back connection of
SONET/SDH framers (if retiming is enabled in the transmit direction), or connections to mapper devices.
Each receive Telecom Bus interface of the SONET/SDH framer consists of the following outputs: 8-bit data
bus (RXTB#DATA(7:0)), clock (RXTB#CLK), SPE indication (RXTB#SPE), C1J1 indication (RXTB#C1J1),
parity (RXTB#PAR), and a failure indication (RXTB#FAIL), where # = 1-4. All of the receive Telecom Bus
ports operate at 19.44 MHz.
When an STM-4c or STS-12c is processed, the four receive Telecom Buses operate in unison as one Tele-
com Bus interface. The C1J1, SPE, clock, and FAILURE outputs are identical. RXTB1DATA(7) is the MSB
and is the first bit received, while RXTB4DATA(0) is the LSB and is the last bit received.
The subsections that follow summarize the functionality of the receive Telecom Bus interface signals.
The receive Telecom Bus clock output (RXTB#CLK, where # = 1-4) is used to clock out the receive Telecom
Bus output signals from the SONET/SDH framer. The clock edge on which the Telecom Bus signals are
clocked out is programmable on a per Telecom Bus basis via the CKINV# control bits. See Functional Rela-
tionship of the Receive Telecom Bus Signals.
Functional Relationship of the Receive Telecom Bus Signals Subframe 1 is shown
RXTB#CLK
C11
J1
RXTB#DATA(7:0)
(Output)
TOH
RXTB#SPE
(Output)
RXTB#C1J1
(Output)
CPOS = 1
RXTB#C1J1
(Output)
CPOS = 0
Notes:
1. Parity and Failure outputs are not shown.
2. The relationship between J1 and the SPE signals is shown for reference purposes only,
and will be a function of the pointer offset.
3. There is a CPOS control bit for each receive Telecom Bus in the OR#Conf13 registers.
ssframer.01
8/27/99
Block Diagram and Block Descriptions
Page 23 of 279
IBM [ IBM ]
