IBM3009K2672
IBM SONET/SDH Framer
Receive UTOPIA Level 2+ Interface Operation for Non-Transparent Mode (16-Byte Chunks)
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
RXUCLK1
(Input)
RXUADDR(4:0)
(Inputs)
N
M
M
Chunk 1 of PHY N
Chunk 2 of PHY N
Chunk 1 of PHY M
RXUDATA(15:8)
(Outputs)
RXUDATA(7:0)
(Outputs)
RXENB
(Input)
RXSOC
(Output)
RXSOFO
(Output)
RXEOFO
(Output)
RXMSO
(Output)
RXABTO
(Output)
RXFCSEO
(Output)
= Fill
The previous figure shows the transfer of frames across the receive UTOPIA Level 2+ interface. The
RXCLAV(0), and RXPRTY signals are omitted to avoid clutter. The polling and selection of PHYs is identical
to that in the ATM mode operation which is also described in [UL2v1]. Therefore, RXUADDR(4:0), RXENB,
RXCLAV(0), RXSOC and RXPRTY behave in the same way as their ATM counterparts, but with the excep-
tion that RXCLAV(0) indicates that the SONET/SDH framer has at least a complete chunk of data to transfer.
As stated earlier, a chunk is analogous to a cell. Chunk size is programmable to be either 16, 32, 48, or 64
bytes. The figure shows the transfer of two blocks of frame data as back to back chunks across PHY N and
one complete block and a partial block of frame data across PHY M. The chunk size in this case is 16 bytes.
The first block of frame data transferred across PHY N on clock edges 3-7 had an FCS error, which is flagged
at the end of the frame data by the RXEOFO and RXFCSEO signals being asserted. The second block of
frame data being transferred across PHY N starts in chunk 1 of PHY N but is aborted in chunk 2 of PHY N. All
aborts are signaled by the simultaneous assertion of the RXEOFO, RXMSO, and RXABTO signals (if the
FCSABT control bit is 0) or the simultaneous assertion of the RXEOFO, RXMSO, and RXFCSEO signals (if
the FCSABT control bit is 1). The abort could have occurred due to any of the conditions listed below:
1. Receive FIFO overflow.
2. An illegal sequence (7D7E H) was detected in the data stream.
3. A frame was received that was below the minimum frame length as defined by the MINFL(6:0) bits when
DMINF is set to ‘1’.
4. A frame was received that equaled or exceeded the maximum frame length defined by the MAXFL(15:0)
bits.
Block Diagram and Block Descriptions
Page 18 of 279
ssframer.01
8/27/99
IBM [ IBM ]
