IBM3009K2672
IBM SONET/SDH Framer
• TXUCLK1 - transmit clock input.
• TXUADDR(4:0)- 5-bit transmit MPHY address input.
• TXCLAV(0) - transmit chunk available output signal. There are three other CLAV signals for multi-PHY
ATM applications.
• TXSOC - transmit start of chunk input signal.
• TXUDATA(15:0) - transmit data input.
• TXENB - transmit enable input. This signal is active low.
• TXPRTY - transmit parity input.
• RXUCLK1 - receive clock input.
• RXUADD(4:0) - 5-bit receive MPHY address input.
• RXCLAV(0) - receive chunk available output signal. There are three other CLAV signals for multi-PHY
ATM applications.
• RXSOC - receive start of chunk input signal.
• RXUDATA(15:0) - receive data output.
• RXENB - receive enable input. This signal is active low.
• RXPRTY - receive parity output.
A number of additional signals are provided for frame delineation purposes:
• TXEOFI - transmit End-of- Frame input.
• TXSOFI - transmit Start-of-Frame input.
• TXABTO - transmit abort output.
• TXMSI - transmit most significant byte input.
• RXEOFO - receive End-of- Frame output.
• RXSOFO - receive Start-of-Frame output.
• RXABTO - receive abort output.
• RXMSO - receive most significant byte output.
• RXFCSEO - receive FCS error output. (Both abort and FCS indications can optionally be provided as out-
puts on this pin.)
Only multi-PHY handshaking is supported when processing PPP Payloads. The UTOPIA Level 2+ behaves
the same whether STM-4/STM-1/STS-12/STS-3c streams are being processed or STM-4c/STS-12c streams
are being processed. The receive and transmit macros operate in parallel as one large PHY to process the
STM-4c/STS-12c streams. As is the case for ATM when STM-4c/STS-12c streams are being processed, the
external transmit and receive address pins should be set to low.
Operation of the UTOPIA Level 2+ interface is very similar to that of multi-PHY UTOPIA. Polling and selection
of PHYs are performed in exactly the same way as described in [UL2v1]. Chunks of frame data are passed
across the data buses. The chunk is analogous to the ATM cell. The TXSOC and RXSOC signals are analo-
gous to the start-of-cell signal. TX/RXCLAV(0) is analogous to the cell available signal. TXPRTY and
RXPRTY are the parity signals. Since PPP frames are of variable size they may or may not fit into a single
chunk transfer. The additional signals as listed above help to facilitate frame delineation.
The format of the data on TXUDATA(0-15) depends on the setting of control bits. If the SONET/SDH framer is
set to calculate and insert 16-bit or 32-bit FCS, TXUDATA(15:0) contains only raw frame data and intra-chunk
fill. The SONET/SDH framer will calculate the FCS and append it to the frame data, insert frame delimiting
flags, and stuff the control escape and flag characters between the frame delimiting flags on a frame by frame
basis. These operations are described in sections 3.1 and 4.2 of [RFC1662]. Inter-frame flags are inserted as
needed. The data can then be optionally scrambled before it is inserted into the SONET/SDH frame. The
SONET/SDH framer can be programmed to have a minimum of either 1 or 2 flags in between frames. If trans-
ssframer.01
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Block Diagram and Block Descriptions
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