IBM3009K2672
IBM SONET/SDH Framer
APH - ATM/PPP Handler
The ATM/PPP Handler is designed to process either four individual 155.52 Mb/s ATM or PPP streams (i.e.,
STM-4/STS-12 or 4 x STM-1/STS-3c) or one single 622.08 Mb/s ATM or PPP stream (i.e., STM-4c/STS-12c).
It should be noted that an STM-4/STS-12 looks like four individual STM-1/STS-3c streams to the APH mac-
ros.
When processing PPP Frame payloads, this macro performs the functions indicated in RFC1619 and
RFC1662 for octet synchronous mapping of PPP into HDLC-Like Framing for transmission over SONET/SDH.
In addition to those functions, the APH block formats the PPP Frame payloads for insertion into the ACB as
well as accepting PPP Frame payloads from the ACB. An optional self-synchronous scrambler/descrambler
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with polynomial 1+X is provided for scrambling the HDLC-Like frame stream. PPP Frame data which is
leaving the APH in the transmit direction or entering the APH in the receive direction can be scram-
bled/descrambled under software control.
The APH macro can also perform the TCS Functionality for ATM Cell payloads such as HEC generation/veri-
fication, cell scrambling/descrambling, as well as HEC-based Cell Delineation.
ACB - ATM Cell Buffer
The ACB is a FIFO, four ATM cells deep, that is between the UTOPIA interface and the APH macros. This
buffer is used to accrue/accept complete cells/chunks in ATM/PPP processing mode. This is because the
SONET/SDH framer is a PHY layer device and only does cell/chunk level handshaking for ATM/PPP applica-
tions. When an STM-4c or STS-12c is processed, the ACB macros work in parallel to create one large FIFO
in the transmit direction and one large FIFO in the receive direction.
UTOPIA Interface
Some additional but brief comments on the interface are provided for ATM and PPP mode operation. The “+”
in UTOPIA LEVEL 2+ indicates that the SONET/SDH framer uses the UTOPIA interface with some added
signals and modifications for transferring PPP data between the SONET/SDH framer and a PPP processing
device, which will be called the “ATM Emulation Layer”.
It should be noted that, since the SONET/SDH framer is a PHY layer device, no switching is performed. There
exists the option of having two 8-bit UTOPIA level 1 interfaces. These interfaces are compliant with [UL1].
When they are used, only two STM-1/STS-3c streams can be terminated. These streams can either be indi-
vidual 155.52 Mb/s streams or they can be contained in an STM-4/STS-12. If the need exists for processing
more than two AU-4/STS-3c SPE or an STM-4c/STS-12c stream, then the UTOPIA level 2 interface option
should be selected. The UTOPIA level 2 interface is compliant with [UL2v1]. When the UTOPIA level 2 inter-
face is selected, up to four STM-1/STS-3c streams can be processed in a single SONET/SDH framer. Each
of the four sets of transmit and receive APH macros are considered to be a PHY. There are 8 registers in the
SONET/SDH framer (1 for each transmit and receive APH macro) that are used to define a unique 5-bit
address to each of the PHYs. When processing an STM-4c/STS-12c stream, the UTOPIA Level 2 interface is
also used. In this case, all of the transmit macros operate in parallel and all of the receive macros operate in
parallel to form two large macros, or PHYs, capable of processing the STM-4c/STS-12c payloads. Further-
more, the transmit and receive address pins of the UTOPIA Level 2 interface should be strapped low to sup-
port the single large PHY.
When the SONET/SDH framer is configured to process PPP payloads, the UTOPIA Level 2+ features are
called into play. The UTOPIA Level 2+ interface is a Multi-PHY (MPHY) interface with the following signals
that are shared with their UTOPIA counterparts:
Block Diagram and Block Descriptions
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ssframer.01
8/27/99
IBM [ IBM ]
