IBM3009K2672
IBM SONET/SDH Framer
Receive ATM/PPP Handler ATM Functions
The receive ATM Transmission Convergence Sublayer Functions (TCSFs) are performed in the receive APH
blocks. Four individual AU-4 streams can be processed, such as in an STM-4/STS-12 or in four individual
STM-1/STS-3c frames. 4 x STM-1/STS-3c looks just like 1 x STM-4/STS-12 to the SONET/SDH framer’s
receive APH blocks. A single 622.08 Mb/s stream with a concatenated payload (i.e., a VC-4-4c) can be han-
dled, such as would be found in an STM-4c/STS-12c frame. A four-cell-deep elastic store (i.e., the ACB) is
provided between each receive APH Block and the UTOPIA Level 1/2/2+ interface(s). When an STM-4c/STS-
12c frame is being received, the four receive APH blocks work in parallel as a single receive APH block.
The ATM TCSF functions in the receive ATM/PPP Handler are implemented per [I.432.1]. ATM cell delinea-
tion is performed according to the algorithm in section 4.3.3.2 of [I.432.1]. Programmable ALPHA and DELTA
registers are provided to allow users to program the thresholds for leaving and entering the SYNC state. Sta-
tus bits are provided for indicating the transition from the SYNC to the HUNT state (i.e., Loss of Cell Delinea-
tion) and for indicating that the cell delineation state machine is in the HUNT, PRESYNC, or SYNC modes of
operation. A control bit (LCD_RDI) can be used to enable automatic Path RDI generation in the transmit G1
byte when loss of cell delineation is detected and sustained. Self-synchronizing cell descrambling is per-
formed per section 4.3.4.1 of [I.432.1]. The ATM cell header is checked and error detection/correction is per-
formed according to sections 4.3.2.1 and 4.3.2.2 in [I.432.1]. Single-bit errors can be corrected or not as
enabled via a control bit (NCorHECEr). The coset (i.e., offset) byte of the HEC is user programmable and
defaults to 01010101. Provision is made for additional control bits to:
• Enable the HEC checking state machine to stay in correction mode until the SYNC state is left, or to tran-
sition to the detection mode when a HEC error is detected.
• Allow/prevent IDLE cells to be written to the ACB FIFO.
• Enable/disable ATM cell payload descrambler.
• Enable/disable ATM cells with HEC errors from being written into the ACB FIFO.
• Enable/disable HEC error detection.
An Idle/Unassigned cell filter is provided whereby the five header and payload bytes can be defined so that
cells meeting the criteria are identified as Idle/Unassigned cells and can be optionally discarded. Two 24-bit
long counters are provided for counting received idle cells and ATM cells. Three 16-bit long counters with pro-
grammable thresholds (to signal an interrupt when the respective counters exceed the threshold) are pro-
vided for counting HEC errors, corrected HEC errors, and ATM cells that were discarded due to the receive
ACB FIFO being full. When a receive loopback is enabled, no counting is performed.
Transmit/Receive ATM/PPP Handler Features
Four independent PPP macros can be used to map/extract PPP into/from SONET/SDH Frames per
[RFC1619] and [RFC1662] for STM-1, STS-3c, STM-4, STS-12, STM-4c, and STS-12c applications. A frame
interface called UTOPIA Level 2+ based on the existing UTOPIA Level 2 interface is provided for transferring
frame data on a single-PHY or multi-PHY interface between the SONET/SDH framer and a packet switch.
Frames are transferred across the UTOPIA Level 2+ interface in programmable length chunks of either 16,
24, 32, or 64 bytes.
Transmitted frame data is processed per [RFC1662] and [RFC1619] as follows:
• Either a 16-bit or 32-bit FCS is calculated over the frame data per [RFC1662].
• FCS calculation can be disabled through control bits.
• Transparent mode can be enabled where chunks are mapped directly into the transmit SONET/SDH
frame.
Operation
ssframer.01
8/27/99
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