IBM3009K2672
IBM SONET/SDH Framer
Concatenation Indication State Machine
N x inv_point
CONC
3 x AIS_ind
3 x conc_ind
3 x conc_ind
3 x AIS_ind
LOPC
AISC
N x inv_point
Eight-bit counters are provided for counting positive and negative justification events, as well as NDF events.
Status bits are provided for indicating the detection of negative justification, positive justification, NDF, invalid
pointer, new pointer, and concatenation indication. When the LOP or LOPC states are entered as indicated in
the two previous figures, the LOP interrupt request bit in the corresponding OR#IRQ2 register will be set.
Likewise, if the AIS or AISC states are entered, the corresponding HPAIS interrupt request bit will become
set.
Transmit ATM/PPP Handler ATM Functions
The transmit ATM Transmission Convergence Sublayer Functions (TCSFs) are performed in the transmit
APH blocks. Four individual AU-4 streams can be supported, such as in an STM-4/STS-12 or in four individ-
ual STM-1/STS-3c frames. 4 x STM-1/STS-3c looks just like 1 x STM-4/STS-12 to the SONET/SDH framer’s
transmit APH blocks. A single 622.08 Mb/s stream with a concatenated payload (i.e., a VC-4-4c) can be han-
dled, such as would be found in an STM-4c/STS-12c frame. A four-cell-deep elastic store (i.e., the ACB) is
provided between each transmit APH Block and the UTOPIA Level 1/2/2+ interface(s). When an STM-4c/
STS-12c frame is being generated, the four transmit APH blocks work in parallel as a single transmit APH
block. Idle cells per [I.432] or unassigned cells per [I.361] are provided towards the MSA Layer (i.e., the SFH
blocks) when no ATM cells are available. Generation of Idle/Unassigned cells can be enabled or disabled via
a control bit. The header bytes of Idle/Unassigned Cells can be programmed via on-chip registers. Payload of
Idle/Unassigned cells can be programmed such that:
• Each payload byte of a cell is the same value in the range 0-255, and is configured through the micropro-
cessor interface.
• An incrementing pattern is placed in all the payload bytes of each cell, e.g., all of the payload bytes in a
cell are M, all of the payload bytes in the next cell are M+1, etc.
• An incrementing pattern can be placed in each payload byte of a cell where each successive payload
byte contains a value that is one greater than the value of the previous byte.
The HEC calculation for Idle/Unassigned or ATM layer Cells can be enabled or disabled via software control.
The HEC can be corrupted under microprocessor control via on-chip mask registers for test purposes. A self-
43
synchronous scrambler of polynomial 1+X is provided to scramble the payloads of the transmitted cells.
24-bit counters are provided to count generated idle/unassigned cells and ATM Layer cells read from the
elastic store. An 8-bit counter is provided for counting corrupted ATM Layer cells read from the elastic store.
ssframer.01
8/27/99
Operation
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