Datasheet
PowerPC 970FX RISC Microprocessor
2
3.10 I C and JTAG
3.10.1 I2C Bus Timing Information
The I2C-bus specification can be downloaded from the NXP Web site at http://www.nxp.com/prod-
ucts/interface_control/i2c/.
The PowerPC 970FX I2C bus is limited to a speed of 50 kHz for the standard-mode timing specification and
does not support the high-speed (Hs-mode) or fast-mode timing.
The PowerPC 970FX I2C pins are limited to OVDD voltages. Level shifting or pullups or both might be
required to interface to higher voltage devices. See The I2C-bus specification for recommendations on level
shifting and pullups.
Note: To avoid problems in determining the correct pull-up resistor value, wiring level-shifted
PowerPC 970FX I2C bus pins together with non-PowerPC 970FX parts in a system is discouraged. Each
PowerPC 970FX should have its own private level shifter.
3.10.2 IEEE 1149.1 ac Timing Specifications
Table 3-24 provides the IEEE 1149.1 JTAG ac timing specifications as defined in Figure 3-10 on page 42 and
Figure 3-11 on page 43. The five JTAG signals are listed here:
• TDI (test data in)
• TDO (test data out)
• TMS (test mode select)
• TCK (test clock)
• TRST (test reset)
Note: The following recommendations address some of the PowerPC 970FX’s nonstandard IEEE ac timing
implementations:
• See Section 3.10.3 I2C and JTAG Considerations on page 43 to determine pullups and pulldowns for
configuration of TCK, TDI, and TMS.
• JTAG scan chains should not be daisy chained in systems using multiple PowerPC 970FX’s in multipro-
cessor configurations if I2C is supported. The JTAG scan chains should be connected in parallel (all TCKs
tied together, all TDIs tied together, and so forth) and use separate TMS inputs to select each 970 pro-
cessor for JTAG access.
• JTAG operations require that the core clock be operating normally with the PLL in bypass mode. CLKIN
and CLKIN must receive at least 16 pulses for TCK down level and 16 pulses for TCK up level.
Version 2.5
Electrical and Thermal Characteristics
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March 26, 2007
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