Datasheet
PowerPC 970FX RISC Microprocessor
Figure 3-11 provides the test access port timing diagram.
Figure 3-11. Test Access Port Timing Diagram
TCK
4
5
TDI, TMS
Input Data (Valid)
6
Output Data (Valid)
TDO
7
TDO
TDO
8
Output Data (Not valid)
Note: The legend for this figure is provided in Table 3-24 JTAG ac Timing Specifications (Dependent on
SYSCLK) on page 42.
3.10.3 I2C and JTAG Considerations
For systems using only JTAG, TDO should be pulled up (tied to OVDD), and the I2C data and clock pins
should also be tied to OVDD. For systems using only I2C, the signals TCK, TMS, TDO, and TDI should be
pulled down. If the system needs to support both JTAG and I2C access, pull-down resistors must be
connected to the JTAG pins. These resistors maintain the correct state on the JTAG pins when I2C access is
active. These pull-down resistors must be able to be overdriven for JTAG operation. Additionally, the JTAG
driver hardware connected to the 970FX should drive its outputs low (on TCK, TMS, TDI) when JTAG is idle.
Note: TRST should always be pulled up to OVDD on the PowerPC 970FX.
3.10.4 Boundary Scan Considerations
The PowerPC 970FX does not support the boundary scan description language (BSDL) standard for imple-
menting boundary scan testing. The IBM technical library contains an application note titled PowerPC 970FX
Boundary Scan that describes a method of producing the equivalent function.
Version 2.5
Electrical and Thermal Characteristics
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March 26, 2007
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