Datasheet
PowerPC 970FX RISC Microprocessor
3.8 Mode Select Input Timing Specifications
This section provides timing specifications for the mode-select pins. These pins are sampled by HRESET.
Table 3-21 provides the input ac timing specifications as defined in Figure 3-8 on page 38. The mode-select
signals and debug pins are listed in Table 3-22 on page 39 and Table 3-23 on page 39.
Table 3-21. Input ac Timing Specifications
Value
Callout
Number
Characteristic
Unit
Notes
Minimum
>1
Maximum
1
HRESET width
—
—
—
—
—
—
ms
4
4
2
BYPASS width
200
20
μs
3
Mode select signal setup
Processor clocks
Processor clocks
Processor clocks
Processor clocks
1, 5
1
4
Mode select inputs hold time
PLL control signal setup
1000
20
5
6
2, 3
2, 3
PLL control inputs hold time
20
Notes:
1. Mode select pins must not change level sooner than 20 processor clocks before the falling edge of HRESET and must be held for
a minimum of 1000 processor clocks after the rising edge of HRESET.
2. PLL control pins must not change level earlier than 20 processor clocks before the rising edge of BYPASS and must be held for a
minimum of 20 processor clocks after the rising edge of HRESET.
3. PLL control inputs must not change while HRESET is low.
4. For timing diagrams, see Figure 3-8 on page 38 and Figure 3-9 on page 40.
5. Guaranteed by design and not tested.
Version 2.5
Electrical and Thermal Characteristics
Page 37 of 78
March 26, 2007
IBM [ IBM ]
