Datasheet
PowerPC 970FX RISC Microprocessor
Figure 3-8. HRESET and BYPASS Timing Diagram
All power supply voltages stable and
SYSCLK ramp up completed
Power
> 100 ns before INITCORE
1
SRESET
500 μs
100 μs
> 1 ms
HRESET
200 μs
800 μs
800 μs
2
BYPASS
PLL_LOCKED
PLL stable
4
3
Mode Select Inputs 1
5
6
PLL Control Inputs2
Reference
Time A
Notes:
1. These timings refer to the following pins: BUS_CFG(0:2), PROCID(0:2).
2. These timings refer to the following pins: CKTERM_DIS, PLL_MULT, and PLL_RANGE(1:0).
These pins can only be changed by driving HRESET and BYBASS low.
3. HRESET and BYPASS can be low during initial program load stages and need not change during powerup before reference time A.
4. PLL control inputs must not change while HRESET is low.
5. The legend for this figure is provided by callout number in Table 3-21 on page 37.
Electrical and Thermal Characteristics
Page 38 of 78
Version 2.5
March 26, 2007
IBM [ IBM ]
