Datasheet
PowerPC 970FX RISC Microprocessor
Table 3-24. JTAG ac Timing Specifications (Dependent on SYSCLK)
Callout
Number
Characteristic
Minimum
Maximum
Unit
Notes
—
1
2
3
4
5
6
7
8
TCK frequency of operation
TCK cycle time
—
32
15
0
1/16
—
—
2
Core processor frequency
1, 5
2, 5
2, 5
3, 5
5
Processor clocks
TCK clock pulse width
Processor clocks
TCK rise and fall times
ns
ns
ns
ns
ns
ns
TMS, TDI data setup time
TMS, TDI data hold time
TCK to TDO data valid
0
—
—
12
9
15
2.5
3
5
4, 5
3, 5
5
TCK to TDO high impedance
TCK to output data not valid (output hold)
0
—
Notes:
1. TCK frequency is limited by the core processor frequency.
2. Processor clock cycles.
3. Guaranteed by characterization and not tested.
4. The minimum specification is guaranteed by characterization and not tested.
5. The JTAG timings are dependent on an active SYSCLK.
6. For a timing diagram, see Figure 3-10 and Figure 3-11 on page 43.
Figure 3-10. JTAG Clock Input Timing Diagram
1
2
2
TCK
3
VM
VM
VM
3
VM = Midpoint Voltage (0V /2)
DD
Note: The legend for this figure is provided by callout number in Table 3-24.
Electrical and Thermal Characteristics
Page 42 of 78
Version 2.5
March 26, 2007
IBM [ IBM ]
