Data Sheet
Preliminary
PowerPC 970FX
5.6 Input-Output Usage
Table 5-8 provides details on the input-output usage of the PowerPC 970FX signals.
5.6.1 Chip Signal I/O and Test Pins
The system signal names, debug and test pins are shown in Table 5-8. There are 172 total chip pads. These
include three power/capacitance pins.
Table 5-8. Input/Output Signal Descriptions
Pin Name
ADIN(0:43)
Width
44
In/Out
In
System/Debug Function
Notes
—
System: EI Address or data and control information
ADOUT(0:43)
AFN
44
Out
System: Elastic Interface (EI) Address or data and control information out
—
1
Out
Pin AFN is now a spare output pin
5
ANALOG_GND
ATTENTION
1
1
1
1
1
Analog ground
—
—
—
1
Out
In
Debug: Signal from PowerPC 970FX
Analog power supply
AV
DD
AVP_RESET
BI_MODE
In
Manufacturing test use only
Dedicated manufacturing
In
1
Bus configuration select. Select bus frequency division factor:
Divide CPU clock by 2, 3, 4, 6, 8, 12 or 16.
000 = 2:1
001 = 3:1
010 = 4:1
011 = 6:1
100 = 8:1
101 = 12:1
110 = 16:1
111 = Invalid
BUS_CFG(0:2)
3
In
3, 8
BYPASS
1
1
1
In
In
In
Used to bypass the PLL.
1
C1_UND_GLOBAL
C2_UND_GLOBAL
Notes:
Debug: adjusts C1 clock to internal latches, not used for normal operation
Debug: adjusts C2 clock to internal latches, not used for normal operation
10
10
1. These are test signals for factory use only and must be pulled up to OVDD for normal processor operation.
2
2. For I C or JTAG operation, must be pull down with a 10K resistor to GND. Refer to Section 3.10.3.
3. Bus ratios 8:1 and 16:1 are not supported for Elastic Input (EI) functionality.
4. These are test signals for factory use only and must be pulled down to GND for normal processor operation.
5. This signal should not be connected.
6. These pins may be used to measure on-chip voltage drop and noise. They should be connected to a backside probe point
immediately behind the module. They should not be connected to GND and V planes.
DD
7. BiDi = Bidirectional.
8. Using the 4:1 or 12:1 ratio with multiplier of 12 will limit the use of the PowerTune to (freq)/2.
9. The PLL_MULT and PLL_RANGE(1:0) bits may be overwritten by JTAG commands and the BUS_CFG bits may be changed by
SCOM commands during the POR (power on reset) sequence. Refer to the POR Application Note for more details
10. Must be pull down with a 10K resistor to GND
System Design Information
October 14, 2005
Page 65 of 74
IBM [ IBM ]
