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IBM25PPC970FX6TR348ET 参数 Datasheet PDF下载

IBM25PPC970FX6TR348ET图片预览
型号: IBM25PPC970FX6TR348ET
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microprocessor, 64-Bit, 2000MHz, CMOS, CBGA576, 25 X 25 MM, 1 MM PITCH, ROHS COMPLIANT, CERAMIC, BGA-576]
分类和应用: 时钟外围集成电路
文件页数/大小: 74 页 / 3280 K
品牌: IBM [ IBM ]
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Data Sheet  
PowerPC 970FX  
Preliminary  
Table 5-8. Input/Output Signal Descriptions (Continued)  
Pin Name  
Width  
In/Out  
In  
System/Debug Function  
Notes  
SRESET  
1
2
2
2
2
1
System: Soft reset  
SRIN(0:1)  
In  
System: EI Snoop response in  
SRIN(0:1)  
In  
System: EI Inverse of Snoop response in  
System: EI Snoop Response out  
System:EI Inverse of Snoop Response out  
Manufacturing test use only  
SROUT(0:1)  
SROUT(0:1)  
SYNC_ENABLE  
Out  
Out  
In  
4
SYSCLK  
SYSCLK  
2
1
1
1
1
In  
In  
System Reference clock (differential input)  
TBEN  
TCK  
TDI  
System: Time base enable  
JTAG: Test Clock which is separate from system clock. Controls all Test  
Access Port functions  
In  
2
2
In  
JTAG: Serial input used to feed test data and Test Access Port instructions.  
JTAG: Serial output used to extract data from the chip under test control.  
TDO  
Out  
THERM_INT  
TMS  
1
1
1
In  
In  
In  
System: External thermal interrupt when low  
JTAG: Select used to control the operation of the JTAG state machine  
Initiate trace collection from outside  
TRIGGERIN  
Signal to indicate internal trace collection has begun.  
TRIGGEROUT  
1
1
Out  
In  
2
TRST  
JTAG: Asynchronous Reset for the JTAG state machine.  
Notes:  
1. These are test signals for factory use only and must be pulled up to OVDD for normal processor operation.  
2
2. For I C or JTAG operation, must be pull down with a 10K resistor to GND. Refer to Section 3.10.3.  
3. Bus ratios 8:1 and 16:1 are not supported for Elastic Input (EI) functionality.  
4. These are test signals for factory use only and must be pulled down to GND for normal processor operation.  
5. This signal should not be connected.  
6. These pins may be used to measure on-chip voltage drop and noise. They should be connected to a backside probe point  
immediately behind the module. They should not be connected to GND and V planes.  
DD  
7. BiDi = Bidirectional.  
8. Using the 4:1 or 12:1 ratio with multiplier of 12 will limit the use of the PowerTune to (freq)/2.  
9. The PLL_MULT and PLL_RANGE(1:0) bits may be overwritten by JTAG commands and the BUS_CFG bits may be changed by  
SCOM commands during the POR (power on reset) sequence. Refer to the POR Application Note for more details  
10. Must be pull down with a 10K resistor to GND  
System Design Information  
October 14, 2005  
Page 68 of 74  
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