Data Sheet
Preliminary
PowerPC 970FX
5.4 Decoupling Recommendations
Capacitor decoupling is required for the PowerPC 970FX. Decoupling capacitors act to reduce high
frequency chip switching noise and provide localized bulk charge storage to reduce major power surge
effects. Guidelines for high frequency noise decoupling will be provided. Bulk decoupling requires a more
complete understanding of the system and system power architecture which precludes discussion in this
document.
High frequency decoupling capacitors should be located as close as possible to the processor with low lead
inductance to the ground and voltage planes.
The recommended placement of the decoupling capacitors is shown in Figure 5-2. The decoupling layout is
divided into three groups:
• Group 1 is located in the center of the package and under the PowerPC 970FX die.
• Group 2 includes Group 1 and is located in the center of the package and under the PowerPC 970FX die.
• Group 3, located adjacent to Group 2 (which includes Group 1), lays under the module footprint. Vias for
the decoupling capacitors should ideally be through vias with via in pad for low impedance.
The recommended decoupling capacitor specifications are provided in Table 5-4.
Table 5-4. Recommended Decoupling Capacitor Specifications
0402 size (1.00 x 0.50 mm)
100 nF
Y5V or X7R dielectric
10V voltage rating
The minimum recommended number of decoupling capacitors for Group 1 and Group 2 are provided
inTable 5-5.
Table 5-5. Recommended Minimum Number of Decoupling Capacitors
Recommended Minimum Number of Decoupling Capacitors
(See Figure 5-2 on page 62 )
Group 2
Group 1
Group 3
Includes all balls in the area defined
by a dotted-green rectangle from F7 to
W18. Also includes all balls in Group
1.
Includes all balls in the area defined by a
red rectangle from H9 to U16.
Includes all balls on the chip not in
Groups 1 and 2.
Minimum of 80 caps
Minimum of 35 V -GND
Minimum of 40:
DD
(including all 12 OV
)
33 V -GND
DD
Minimum of 4 OV -GND
DD
DD
7 OV -GND
DD
Note: Add additional decoupling capacitors to improve noise performance.
5.4.1 Using the KVPRBVDD and KVPRBGND Pins
The PowerPC 970 features one pair of VDD and GND pins to assist in analyzing on-chip noise and voltage
drop. These pins should not be connected into the normal VDD and GND planes, but should be brought out to
test pads by traces that are as short as possible. An oscilloscope can be used on these test pads to measure
on-chip VDD noise and thus to verify the decoupling and voltage regulation in a design. If these pins are not
needed, they should be left unconnected.
System Design Information
October 14, 2005
Page 61 of 74
IBM [ IBM ]
