Data Sheet
Preliminary
PowerPC 970FX
Table 5-8. Input/Output Signal Descriptions (Continued)
Pin Name
PLL_LOCK
Width
1
In/Out
Out
System/Debug Function
Notes
—
Indicates PLL has locked
Select PLL multiplication factor:
0 = multiply ref frequency by 12
1 = multiply ref frequency by 8
PLL_MULT
1
In
9
Select PLL frequency range
00 = 1 GHz to 1.4 GHz range
01 = 1.2 GHz to 1.8 GHz range
10 = 1.6 GHz to 2.2 GHz range
11 = Reserved
PLL_RANGE(1:0)
2
In
9
PLLTEST
1
1
In
Manufacturing test use only
4
PLLTESTOUT
PROCID(0:1)
Out
Measure PLL output (divide by 64)
—
3
3
In
In
System: Processor id maximum eight processors
System: Processor id maximum eight processors
—
—
PROCID(0:2)
PSRO_Enable
PSRO0
1
1
1
Out
Out
In
Manufacturing test use only
5
5
Manufacturing test use only
PSYNC
System: Phase Synchronization from North Bridge
—
System: Phase synchronization signal for observation that processors are
in sync.
PSYNC_OUT
1
2
1
Out
In
—
—
—
PULSE_SEL(0:2)
QACK
In
System: Acknowledge of quiesce from system
QREQ
1
1
1
1
1
Out
In
System: Request from processor to quiescence system (nap mode)
Manufacturing test use only
—
4
RAMSTOP_ENABLE
RI
In
Dedicated Manufacturing
1
SPARE
SPARE2
Notes:
In/Out
In/Out
—
—
1. These are test signals for factory use only and must be pulled up to OVDD for normal processor operation.
2
2. For I C or JTAG operation, must be pull down with a 10K resistor to GND. Refer to Section 3.10.3.
3. Bus ratios 8:1 and 16:1 are not supported for Elastic Input (EI) functionality.
4. These are test signals for factory use only and must be pulled down to GND for normal processor operation.
5. This signal should not be connected.
6. These pins may be used to measure on-chip voltage drop and noise. They should be connected to a backside probe point
immediately behind the module. They should not be connected to GND and V planes.
DD
7. BiDi = Bidirectional.
8. Using the 4:1 or 12:1 ratio with multiplier of 12 will limit the use of the PowerTune to (freq)/2.
9. The PLL_MULT and PLL_RANGE(1:0) bits may be overwritten by JTAG commands and the BUS_CFG bits may be changed by
SCOM commands during the POR (power on reset) sequence. Refer to the POR Application Note for more details
10. Must be pull down with a 10K resistor to GND
System Design Information
October 14, 2005
Page 67 of 74
IBM [ IBM ]
