Data Sheet
PowerPC 970FX
Preliminary
Table 5-8. Input/Output Signal Descriptions (Continued)
Pin Name
CHKSTOP
Width
In/Out
System/Debug Function
System: Checkstop in/out
Notes
7
OD
/BiDi
1
1
2
CKTERM_DIS
In
In
Disable internal termination in clock receiver
—
CLKIN
CLKIN
System: EI Clock In; differential clock to the processor.
—
CLKOUT
CLKOUT
2
Out
System: EI Differential clock to the bus
—
DI2
1
1
In
In
Dedicated Manufacturing
1
EI_DISABLE
GPULDBG
Debug: Disable elastic interface
—
1
1
1
In
In
Debug: POR debug mode select.
System: Power on reset
—
—
7
HRESET
I2CCK
OD
/BiDi
2
System: I C signal clock
OD
/BiDi
2
I2CDT
1
1
1
System: I C interface data
7
2
I2CGO
INT
OD
In
Debug: Handshake signal to arbitrate JTAG/I C access
—
—
System: External interrupt when low
LSSD_SCAN_ENABLE
KVPRBVDD
1
1
1
1
1
In
In
In
In
In
Manufacturing test use only
4
6
6
4
4
V
test point
DD
KVPRBGND
GND test point
LSSD_STOP_ENABLE
LSSD_STOPC2_ENABLE
Manufacturing test use only
Manufacturing test use only
LSSD_STOPC2STAR_ENA
BLE
1
In
Manufacturing test use only
4
LSSDMODE
MCP)
1
1
In
In
Manufacturing test use only
4
System: Machine check interrupt
—
Notes:
1. These are test signals for factory use only and must be pulled up to OVDD for normal processor operation.
2
2. For I C or JTAG operation, must be pull down with a 10K resistor to GND. Refer to Section 3.10.3.
3. Bus ratios 8:1 and 16:1 are not supported for Elastic Input (EI) functionality.
4. These are test signals for factory use only and must be pulled down to GND for normal processor operation.
5. This signal should not be connected.
6. These pins may be used to measure on-chip voltage drop and noise. They should be connected to a backside probe point
immediately behind the module. They should not be connected to GND and V planes.
DD
7. BiDi = Bidirectional.
8. Using the 4:1 or 12:1 ratio with multiplier of 12 will limit the use of the PowerTune to (freq)/2.
9. The PLL_MULT and PLL_RANGE(1:0) bits may be overwritten by JTAG commands and the BUS_CFG bits may be changed by
SCOM commands during the POR (power on reset) sequence. Refer to the POR Application Note for more details
10. Must be pull down with a 10K resistor to GND
System Design Information
October 14, 2005
Page 66 of 74
IBM [ IBM ]
